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- Soeleman, H; Roy, K; Paul, BC

Robust subthreshold logic for ultra-low power operation*IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS*

- Filanovsky, IM; Allam, A

Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits*IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS*

- Leroy, Y; Cordan, AS; Goltzene, A

Reduction of the threshold voltage dispersion in nanometer-sized arrays showing Coulomb blockade*MATERIALS SCIENCE & ENGINEERING C-BIOMIMETIC AND SUPRAMOLECULAR SYSTEMS*

- Filanovsky, IM; Allam, A; Lim, ST

Temperature dependence of output voltage generated by interaction of threshold voltage and mobility of an NMOS transistor*ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING*

- Hayashi, H; Miura, N; Komatsubara, H; Fukuda, K

A simplified process modeling for reverse short channel effect of threshold voltage of MOSFET*IEICE TRANSACTIONS ON ELECTRONICS*

- Kuroda, T

Low power CMOS design challenges*IEICE TRANSACTIONS ON ELECTRONICS*

- Ogasawara, S; Yoon, SM; Ishiwara, H

Fabrication and characterization of 1T2C-type ferroelectric memory cell*IEICE TRANSACTIONS ON ELECTRONICS*

- Kranti, A; Haldar, S; Gupta, RS

An analytical two-dimensional model for an optically controlled thin-film fully depleted surrounding/cylindrical-gate (SGT) MOSFET*MICROWAVE AND OPTICAL TECHNOLOGY LETTERS*

- Choi, YK; Ha, DW; King, TJ; Hu, CM

Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain*IEEE ELECTRON DEVICE LETTERS*

- Lee, MC; Jung, SH; Song, IH; Han, MK

A new poly-Si TFT structure with air cavities at the gate-oxide edges*IEEE ELECTRON DEVICE LETTERS*

- Kalra, E; Kumar, A; Haldar, S; Gupta, RS

A semi-empirical approach to analyze small geometry effects in LDD MOSFETs*MICROELECTRONIC ENGINEERING*

- Choi, C; Yatsuzuka, K; Asano, K

Dynamic motion of a conductive particle in viscous fluid under DC electricfield*IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS*

- Pio, F; Gomiero, E

Select transistor modulated cell array structure test application in EEPROM process reliability*SOLID-STATE ELECTRONICS*

- Ryou, CR; Hwang, SW; Shin, H; Lee, CH; Park, YJ; Min, HS

Three-dimensional simulation of discrete oxide charge effects in 0.1 mu m MOSFETs*SOLID-STATE ELECTRONICS*

- Ortiz-Conde, A; Cerdeira, A; Estrada, M; Sanchez, FJG; Quintero, R

A simple procedure to extract the threshold voltage of amorphous thin filmMOSFETs in the saturation region*SOLID-STATE ELECTRONICS*

- Kar, GS; Ray, SK; Kim, T; Banerjee, SK; Chakrabarti, NB

Estimation of hole mobility in strained Si1-xGex buried channel heterostructure PMOSFET*SOLID-STATE ELECTRONICS*

- Godoy, A; Lopez-Villanueva, JA; Jimenez-Tejada, JA; Palma, A; Gamiz, F

A simple subthreshold swing model for short channel MOSFETs*SOLID-STATE ELECTRONICS*

- Kranti, A; Haldar, S; Gupta, RS

An accurate 2D analytical model for short channel thin film fully depletedcylindrical/surrounding gate (CGT/SGT) MOSFET*MICROELECTRONICS JOURNAL*

- Ren, HX; Hao, Y

The influence of doping density on short channel effects immunity in deep sub-micron grooved-gate PMOSFETs*MICROELECTRONICS JOURNAL*

- Edgcombe, CJ; Valdre, U

Microscopy and computational modelling to elucidate the enhancement factorfor field electron emitters*JOURNAL OF MICROSCOPY-OXFORD*

- Cho, YH; Kim, BK

Electro-optic properties of CO2 fixed-polymer/nematic LC composite films*JOURNAL OF APPLIED POLYMER SCIENCE*

- Mayergoyz, ID; Andrei, P

Statistical analysis of semiconductor devices*JOURNAL OF APPLIED PHYSICS*

- Chopra, S; Gupta, RS

Cut-off frequency and transit time analysis in short geometry polysilicon thin-film transistors*INTERNATIONAL JOURNAL OF ELECTRONICS*

- Mayergoyz, ID; Andrei, P; Filipovich, I

Analysis of random dopant-induced effects through numerical solution of randomly perturbed nonlinear Poisson equation*IEEE TRANSACTIONS ON MAGNETICS*

- Adan, AO; Higashi, K

OFF-state leakage current mechanisms in BulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Yagishita, A; Saito, T; Nakajima, K; Inumiya, S; Matsuo, K; Shibata, T; Tsunashima, Y; Suguro, K; Arikado, T

Improvement of threshold voltage deviation in damascene metal gate transistors*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Versari, R; Esseni, D; Falavigna, G; Lanzoni, M; Ricco, B

Optimized programming of multilevel flash EEPROMs*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Lau, MM; Chiang, CYT; Yeow, YT; Yao, ZQ

A new method of threshold voltage extraction via MOSFET gate-to-substrate capacitance measurement*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Jurczak, M; Skotnicki, T; Gwoziecki, R; Paoli, M; Tormen, B; Ribot, P; Dutartre, D; Monfray, S; Galvier, J

Dielectric pockets - A new concept of the junctions for deca-nanometric CMOS devices*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Mishima, Y; Yoshino, K; Takei, M; Sasaki, N

Characteristics of low-temperature poly-Si TFTs on Al/glass substrates*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Hou, YT; Li, MF

Hole quantization effects and threshold voltage shift in pMOSFET - Assessed by improved one-band effective mass approximation*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Zhou, X; Lim, KY

Unified MOSFET compact I-V model formulation through physics-based effective transformation*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Benson, J; D'Halleweyn, NV; Redman-White, W; Easson, CA; Uren, MJ; Faynot, O; Pelloie, JL

A physically based relation between extracted threshold voltage and surface potential flat-band voltage for MOSFET compact modeling*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Cheng, ZY; Ling, CH

Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Miura-Mattausch, M; Suetake, M; Mattausch, HJ; Kumashiro, S; Shigyo, N; Odanaka, S; Nakayama, N

Physical modeling of the reverse-short-channel effect for circuit simulation*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Kanda, K; Nose, K; Kawaguchi, H; Sakurai, T

Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs*IEEE JOURNAL OF SOLID-STATE CIRCUITS*

- Omura, Y

Silicon-on-insulator MOSFET structure for sub-00 nm channel regime and performance perspective*JOURNAL OF THE ELECTROCHEMICAL SOCIETY*

- Sano, N; Tomizawa, M

Random dopant model for three-dimensional drift-diffusion simulations in metal-oxide-semiconductor field-effect-transistors*APPLIED PHYSICS LETTERS*

- Kimura, M; Nozawa, R; Inoue, S; Shimoda, T; Lui, BOK; Tam, SWB; Migliorato, P

Extraction of trap states at the oxide-silicon interface and grain boundary for polycrystalline silicon thin-film transistors*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Hiramoto, T; Takamiya, M; Koura, H; Inukai, T; Gomyo, H; Kawaguchi, H; Sakurai, T

Optimum device parameters and scalability of variable threshold voltage complementary MOS (VTCMOS)*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Lin, HC; Chen, JTY; Wong, SC

A new dual floating gate flash cell for multilevel operation*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Hou, YT; Li, MF

A novel simulation algorithm for Si valence hole quantization of inversionlayer in metal-oxide-semiconductor devices*JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS*

- Iwata, H

Self-consistent calculations of performance parameters in highly doped silicon-on-insulator metal-oxide-semiconductor field-effect transistors*JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS*

- Baccarani, G; Reggiani, S

Performance limits of CMOS technology and perspectives of quantum devices*COMPTES RENDUS DE L ACADEMIE DES SCIENCES SERIE IV PHYSIQUE ASTROPHYSIQUE*

- Gross, WJ; Vasileska, D; Ferry, DK

3D simulations of ultra-small MOSFETs with real-space treatment of the electron-electron and electron-ion interactions*VLSI DESIGN*

- Wang, JP; Xu, NJ; Zhang, TQ; Tang, HL; Liu, JL; Liu, CY; Yao, YJ; Peng, HL; He, BP; Zhang, ZX

Temperature effects of gamma-irradiated metal-oxide-semiconductor field-effect-transistor*ACTA PHYSICA SINICA*

- Chou, JC; Chiang, JL

Study on the amorphous tungsten trioxide ion-sensitive field effect transistor*SENSORS AND ACTUATORS B-CHEMICAL*

- Hatfield, JV; Covington, JA; Gardner, JW

GasFETs incorporating conducting polymers as gate materials*SENSORS AND ACTUATORS B-CHEMICAL*

- Chou, JC; Chiang, JL

Ion sensitive field effect transistor with amorphous tungsten trioxide gate for pH sensing*SENSORS AND ACTUATORS B-CHEMICAL*

- Dai, Y; Jones, KE; Fedirchuk, B; Jordan, LM

Effects of voltage trajectory on action potential voltage threshold in simulations of cat spinal motoneurons*NEUROCOMPUTING*

- Hiramoto, T; Takamiya, M

Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias*IEICE TRANSACTIONS ON ELECTRONICS*

- Kuroda, T; Fujita, T; Hatori, F; Sakurai, T

Variable threshold-voltage CMOS technology*IEICE TRANSACTIONS ON ELECTRONICS*

- Kato, N; Akita, Y; Hiraki, M; Yamashita, T; Shimizu, T; Maki, F; Yano, K

Random modulation: Multi-threshold-voltage design methodology in sub-2-V power supply CMOS*IEICE TRANSACTIONS ON ELECTRONICS*

- Consoli, A; Gennaro, F; Testa, A; Consentino, G; Frisina, F; Letor, R; Magri, A

Thermal instability of low voltage power-MOSFET's*IEEE TRANSACTIONS ON POWER ELECTRONICS*

- Yasuda, Y; Takamiya, M; Hiramoto, T

Threshold voltage fluctuations induced by statistical 'position' and 'number' impurity fluctuations in bulk MOSFETs*SUPERLATTICES AND MICROSTRUCTURES*

- Vasileska, D; Gross, WJ; Ferry, DK

Monte Carlo particle-based simulations of deep-submicron n-MOSFETs with real-space treatment of electron-electron and electron-impurity interactions*SUPERLATTICES AND MICROSTRUCTURES*

- Asenov, A; Slavcheva, G; Brown, AR; Balasubramaniam, R; Davies, JH

Statistical 3D 'atomistic' simulation of decanano MOSFETs*SUPERLATTICES AND MICROSTRUCTURES*

- Majima, H; Ishikuro, H; Hiramoto, T

Experimental evidence for quantum mechanical narrow channel effect in ultra-narrow MOSFET's*IEEE ELECTRON DEVICE LETTERS*

- Lun, Z; Ang, DS; Ling, CH

A novel subthreshold slope technique for the extraction of the buried-oxide interface trap density in fully depleted SOI MOSFET*IEEE ELECTRON DEVICE LETTERS*

- Lebedev, E; Forero, S; Brutting, W; Schwoerer, M

Switching effect in poly(p-phenylenevinylene)*SYNTHETIC METALS*

- Koyama, A; Uchida, M; Aida, T; Kudo, J; Ttsuge, M

Switching well noise modeling and minimization strategy for digital circuits with a controllable threshold voltage scheme*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Chopra, S; Gupta, RS

An analytical model for current-voltage characteristics of a small-geometry poly-Si thin-film transistor*SEMICONDUCTOR SCIENCE AND TECHNOLOGY*

- Shinada, T; Ishikawa, A; Hinoshita, C; Koh, M; Ohdomari, I

Flat-band voltage control of a back-gate MOSFET by single ion implantation*APPLIED SURFACE SCIENCE*

- Chopra, S; Gupta, RS

An analytical model for turn-on characteristics of short channel polycrystalline-silicon thin-film transistor for circuit simulation*MICROELECTRONIC ENGINEERING*

- Shang, HL; White, MH

An ultra-thin midgap gate FDSOI MOSFET*SOLID-STATE ELECTRONICS*

- Liu, XY; Kang, JF; Guan, XD; Han, RQ; Wang, YY

The influence of tunneling effect and inversion layer quantization effect on threshold voltage of deep submicron MOSFETs*SOLID-STATE ELECTRONICS*

- Klos, A; Kostka, A

PREDICTMOS - a predictive compact model of small-geometry MOSFETs for circuit simulation and device scaling calculations*SOLID-STATE ELECTRONICS*

- Ma, YT; Liu, LT; Yu, ZP; Li, ZJ

Characterization and modeling of threshold voltage shift due to quantum mechanical effects in pMOSFET*SOLID-STATE ELECTRONICS*

- Suzuki, K; Sudo, R

Conditions of ion implantation into thin amorphous Si gate layers for suppressing threshold voltage shift*SOLID-STATE ELECTRONICS*

- Ma, YT; Li, ZJ; Liu, LT; Tian, LL; Yu, ZP

Effective density-of-states approach to QM correction in MOS structures*SOLID-STATE ELECTRONICS*

- Nicolett, AS; Martino, JA; Simoen, E; Claeys, C

Simultaneous extraction of the silicon film and front oxide thicknesses onfully depleted SOI nMOSFETs*SOLID-STATE ELECTRONICS*

- Zhang, J; Yuan, JS; Ma, Y

Modeling short channel effect on high-k and stacked-gate MOSFETs*SOLID-STATE ELECTRONICS*

- Ma, Y; Liu, L; Li, Z

Surface layer effective density-of-states (SLEDOS) and its applications inMOS devices modeling*MICROELECTRONICS JOURNAL*

- Ma, YT; Liu, LT; Yu, ZP; Li, ZJ

Thorough analysis of quantum mechanical effects on MOS structure characteristics in threshold region*MICROELECTRONICS JOURNAL*

- Samudra, G; Rajendran, K

Comparative analysis of minimum surface potential and location of barrier peaks in various Si MOSFET devices*INTERNATIONAL JOURNAL OF ELECTRONICS*

- Suzuki, K

Short channel MOSFET model using a universal channel depletion width parameter*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Wang, AW; Saraswat, KC

A strategy for modeling of variations due to grain size in polycrystallinethin-film transistors*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Lin, SC; Kuo, JB; Huang, KT; Sun, SW

A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Oishi, T; Shiozawa, K; Furukawa, A; Abe, Y; Tokuda, Y

Isolation edge effect depending on gate length of MOSFET's with various isolation structures*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Murakami, E; Yoshimura, T; Goto, Y; Kimura, S

Gate length scalability of n-MOSFET's down to 30 nm: Comparison between LDD and non-LDD structures*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Wang, HM; Chan, MS; Wang, YY; Ko, PK

The behavior of narrow-width SOI MOSFET's with MESA isolation*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Lim, BC; Choi, YJ; Choi, JH; Jang, J

Hydrogenated amorphous silicon thin film transistor fabricated on plasma treated silicon nitride*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Lee, YT; Woo, DS; Lee, JD; Park, BG

Threshold voltage reduction model for buried channel PMOSFETs using quasi-2-D Poisson equation*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Suzuki, K

Short channel epi-MOSFET model*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Chopra, S; Gupta, RS

Modeling of short geometry polycrystalline-silicon thin-film transistor*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Gross, WJ; Vasileska, D; Ferry, DK

Ultrasmall MOSFETs: The importance of the full coulomb interaction on device characteristics*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Yasuda, Y; Takamiya, M; Hiramoto, T

Separation of effects of statistical impurity number fluctuations and position distribution on Vth fluctuations in scaled MOSFETs*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Williams, SC; Kim, KW; Holton, WC

Ensemble Monte Carlo study of channel quantization in a 25-nm n-MOSFET*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Zhou, X; Lim, KY; Lim, D

A general approach to compact threshold voltage formulation based on 2-D numerical simulation and experimental correlation for deep-submicron ULSI technology development*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Shin, JS; Chung, IY; Park, YJ; Min, HS

A new charge pump without degradation in threshold voltage due to body effect*IEEE JOURNAL OF SOLID-STATE CIRCUITS*

- Kao, JT; Chandrakasan, AP

Dual-threshold voltage techniques for low-power digital circuits*IEEE JOURNAL OF SOLID-STATE CIRCUITS*

- Sako, T; Furukawa, T; Kaneko, T; Sakaigawa, A; Koden, M

Temperature dependence of practical tau-Vmin mode FLC materials*FERROELECTRICS*

- Yano, H; Hirao, T; Kimoto, T; Matsunami, H

High channel mobility in inversion layer of SiC MOSFETs for power switching transistors*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Koh, R

Simulated threshold voltage adjustment and drain current enhancement in novel striped-gate nondoped-channel fully depleted SOI-MOSFETs*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Inukai, T; Hiramoto, T

Suppression of stand-by tunnel current in ultra-thin gate oxide MOSFETs bydual oxide thickness-multiple threshold voltage CMOS (DOT-MTCMOS)*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Koura, H; Takamiya, M; Hiramoto, T

Optimum conditions of body effect factor and substrate bias in variable threshold voltage MOSFETs*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Kodama, S; Furuta, T; Watanabe, N; Ito, H; Kanda, A; Muraguchi, M; Ishibashi, T

Variable threshold AlGaAs/InGaAs heterostructure field-effect transistors with paired gates fabricated using the wafer-bonding technique*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Ohba, R; Sugiyama, N; Koga, J; Uchida, K; Toriumi, A

Influence of channel depletion on the carrier charging characteristics in Si nanocrystal floating gate memory*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Iba, Y; Taguchi, T; Kumasaka, F; Iizuka, T; Sambonsugi, Y; Aoyama, H; Deguchi, K; Fukuda, M; Oda, M; Morita, H; Matsuda, T; Horiuchi, K; Matsui, Y

Sub-100-nm device fabrication using proximity X-ray lithography at five levels*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Shinada, T; Ishikawa, A; Hinoshita, C; Koh, M; Ohdomari, I

Reduction of fluctuation in semiconductor conductivity by one-by-one ion implantation of dopant atoms*JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS*

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici

Documento generato il 28/10/20 alle ore 00:41:35