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- Zheng, LR; Tenhunen, H

Design and analysis of power integrity in deep submicron system-on-chip circuits*ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING*

- Kikkawa, T

Multilayer interconnect technology for scaling*ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS*

- Mao, JF; Qian, XN; Yuan, ZY

Characteristic analysis of coupled HTS interconnects with two-dimensional FDTD*IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS*

- Martin, LJ; Wong, CP

Chemical and mechanical adhesion mechanisms of sputter-deposited metal on epoxy dielectric for high density interconnect printed circuit boards*IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES*

- Liu, WF; Pecht, MG; Xie, JS

Fundamental reliability issues associated with a commercial particle-in-elastomer interconnection system*IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES*

- Ilumoka, AA

Efficient and accurate crosstalk prediction via neural net-based topological decomposition of 3-D interconnect*IEEE TRANSACTIONS ON ADVANCED PACKAGING*

- Svensson, C; Dermer, GE

Time domain modeling of lossy interconnects*IEEE TRANSACTIONS ON ADVANCED PACKAGING*

- Iwashige, H; Kutulk, G; Hayashi, S; Suzuki, T; Yoshida, T; Abe, T; Oda, M

ULSI interconnect formation using dispersed nanoparticles*SCRIPTA MATERIALIA*

- Liu, PL; Shang, JK

Interfacial segregation of bismuth in copper/tin-bismuth solder interconnect*SCRIPTA MATERIALIA*

- Chu, C; Wong, DF

Closed form solution to simultaneous buffer insertion/sizing and wire sizing*ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS*

- Jin, WJ; Eo, Y; Eisenstadt, WR; Shim, J

Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects*IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS*

- Abramovici, M; Stroud, CE

BIST-based test and diagnosis of FPGA logic blocks*IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS*

- Ismail, YI; Friedman, EG; Neves, JL

Repeater insertion in tree structured inductive interconnect*IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING*

- Goknar, IC; Kutuk, H; Kang, SMS

MOMCO: Method of moment components for passive model order reduction of RLCG interconnects*IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS*

- Liu, Y; Pileggi, LT; Strojwas, AJ

ftd: Frequency to time domain conversion for reduced-order interconnect simulation*IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS*

- Cohen, MI; Allerman, AA; Choquette, KD; Jagadish, C

Electrically steerable lasers using wide-aperture VCSELs*IEEE PHOTONICS TECHNOLOGY LETTERS*

- Liu, YJ; Lin, L; Choi, C; Bihari, B; Chen, RT

Optoelectronic integration of polymer waveguide array and metal-semiconductor-metal photodetector through micromirror couplers*IEEE PHOTONICS TECHNOLOGY LETTERS*

- Casares-Giner, V

Integration of dispatch and interconnect traffic in a land mobile trunkingsystem. Waiting time distributions*TELECOMMUNICATION SYSTEMS*

- Maier, G; Banerjee, S; Haussmann, J; Sezi, R

High-temperature polymers for advanced microelectronics*HIGH PERFORMANCE POLYMERS*

- Miller, DC; Zhang, WG; Bright, VM

Micromachined, flip-chip assembled, actuatable contacts for use in high density interconnection in electronics packaging*SENSORS AND ACTUATORS A-PHYSICAL*

- Liu, CY; Lee, S; Chuang, TJ

Grain boundary crack growth in interconnects with an electric current*MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY*

- Ohki, A; Usui, M; Sato, N; Tanaka, N; Katsura, K; Kagawa, T; Hikita, M; Enbutsu, K; Tohno, S; Ando, Y

Development of 60 Gb/s-class parallel optical interconnection module (ParaBIT-1)*IEICE TRANSACTIONS ON ELECTRONICS*

- Nishiyama, H; Aizawa, M; Sakai, N; Yokokawa, H; Kawada, T; Dokiya, M

Property of (La, Ca)CrO3 for interconnect in solid oxide fuel cell (Part 2) - Durability*JOURNAL OF THE CERAMIC SOCIETY OF JAPAN*

- Ymeri, H; Nauwelaers, B; Maex, K

Distributed inductance and resistance per-unit-length formulas for VLSI interconnects on silicon substrate*MICROWAVE AND OPTICAL TECHNOLOGY LETTERS*

- Ymeri, H; Nauwelaers, B; Maex, K

On the capacitance and conductance calculations of integrated-circuit interconnects with thick conductors*MICROWAVE AND OPTICAL TECHNOLOGY LETTERS*

- Zhang, W; Lee, JH; Bernstein, JB

Energy effect of the laser-induced vertical metallic link*IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING*

- Hohlfelder, RJ; Maidenberg, DA; Dauskardt, RH; Wei, YG; Hutchinson, JW

Adhesion of benzocyclobutene-passivated silicon in epoxy layered structures*JOURNAL OF MATERIALS RESEARCH*

- Wan, PJ; Liu, LW; Yang, YY

Optimal routing based on super topology in optical parallel interconnect*JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING*

- Gungor, MR; Maroudas, D

Modeling of electromechanically-induced failure of passivated metallic thin films used in device interconnections*INTERNATIONAL JOURNAL OF FRACTURE*

- Jin, C; Lin, S; Wetzel, JT

Evaluation of ultra-low-k dielectric materials for advanced interconnects*JOURNAL OF ELECTRONIC MATERIALS*

- Ohba, T

Material and process challenges in 100 nm interconnects module technology and beyond*JOURNAL OF ELECTRONIC MATERIALS*

- Shen, YL

Local Joule heating and overall resistance increase in void-containing aluminum interconnects*JOURNAL OF ELECTRONIC MATERIALS*

- Faust, N; Messler, RW; Khatri, S

Alternatives for joining Si wafers to strain-accommodating Cu for high-power electronics*JOURNAL OF ELECTRONIC MATERIALS*

- Hau-Riege, CS; Hau-Riege, SP; Thompson, CV

Simulation of microstructural evolution induced by scanned laser annealingof metallic interconnects*JOURNAL OF ELECTRONIC MATERIALS*

- Gross, TS; Prindle, CM; Chamberlin, K; bin Kamsah, N; Wu, YY

Two-dimensional, electrostatic finite element study of tip-substrate interactions in electric force microscopy of high density inter-connect structures*ULTRAMICROSCOPY*

- Pendurkar, R; Chatterjee, A; Zorian, Y

Switching activity generation with automated BIST synthesis for performance testing of interconnects*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Cong, J; He, L; Koh, CK; Pan, Z

Interconnect sizing and spacing with consideration of coupling capacitance*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Kuhlmann, M; Sapatnekar, SS

Exact and efficient crosstalk estimation*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Restle, PJ; Ruehli, AE; Walker, SG; Papadopoulos, G

Full-wave PEEC time-domain method for the modeling of on-chip interconnects*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Cong, J; Pan, Z

Interconnect performance estimation models for design planning*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Chang, YW; Lin, JM; Wong, MDF

Matching-based algorithm for FPGA channel segmentation design*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Alpert, CJ; Devgan, A; Kashyap, CV

RC delay metrics for performance optimization*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Chen, LH; Marek-Sadowska, M

Aggressor alignment for worst-case crosstalk noise*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Kahng, AB; Mantik, S; Stroobandt, D

Toward accurate models of achievable routing*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Mo, YY; Chu, C

Hybrid dynamic/quadratic programming algorithm for interconnect tree optimization*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Saxena, P; Liu, CL

Optimization of the maximum delay of global interconnects during layer assignment*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Alpert, CJ; Gandham, G; Hu, J; Neves, JL; Quay, ST; Sapatnekar, SS

Steiner tree optimization for buffers, blockages, and bays*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Cong, J; Koh, CK; Madden, PH

Interconnect layout optimization under higher order RLC model for MCM designs*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Ozkaramanli, H

A comparison of strong and weak distributed transverse coupling between VLSI interconnects*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Beattie, M; Krauter, B; Alatan, L; Pileggi, L

Equipotential shells for efficient inductance extraction*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Hafed, M; Oulmane, M; Rumin, NC

Delay and current estimation in a CMOS inverter with an RC load*IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS*

- Louis, D; Beverina, A; Arvet, C; Lajoinie, E; Peyne, C; Holmes, D; Maloney, D

Cleaning status on low-k dielectric in advanced VLSI interconnect: Characterisation and principal issues*MICROELECTRONIC ENGINEERING*

- Zhu, ZM; Xia, X; Streiter, R; Ruan, G; Otto, T; Wolf, H; Gessner, T

Closed-form formulae for frequency-dependent 3-D interconnect inductance*MICROELECTRONIC ENGINEERING*

- Gonella, R

Key reliability issues for copper integration in damascene architecture*MICROELECTRONIC ENGINEERING*

- Brylewski, T; Nanko, M; Maruyama, T; Przybylski, K

Application of Fe-16Cr ferritic alloy to interconnector for a solid oxide fuel cell*SOLID STATE IONICS*

- Zschech, E; Blum, W; Zienert, I; Besser, PR

Effect of copper line geometry and process parameters on interconnect microstructure and degradation processes*ZEITSCHRIFT FUR METALLKUNDE*

- Wu, W; Yuan, JS

Copper electromigration modeling including barrier layer effect*SOLID-STATE ELECTRONICS*

- Meindl, JD; Chen, Q; Davis, JA

Limits on silicon nanoelectronics for terascale integration*SCIENCE*

- Ymeri, H; Nauwelaers, B; Maex, K

On the modelling of multiconductor multilayer systems for interconnect applications*MICROELECTRONICS JOURNAL*

- Sabelka, R; Selberherr, S

A finite element simulator for three-dimensional analysis of interconnect structures*MICROELECTRONICS JOURNAL*

- Levine, ZH; Grantham, S; Neogi, S; Frigo, SP; McNulty, I; Retsch, CC; Wang, YX; Lucatorto, TB

Accurate pattern registration for integrated circuit tomography*JOURNAL OF APPLIED PHYSICS*

- Yang, XP; Li, ZF

Analysis of power/ground bounces on the conductive planes in high-speed MCMs with a novel systematic method*INTERNATIONAL JOURNAL OF ELECTRONICS*

- Coperich, KM; Morsey, J; Okhmatovski, VI; Cangellaris, AC; Ruehli, DE

Systematic development of transmission-line models for interconnects with frequency-dependent losses*IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES*

- Dounavis, A; Achar, R; Nakhla, M

A general class of passive macromodels for lossy multiconductor transmission lines*IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES*

- Suzuki, M; Miyashita, H; Kamo, A; Watanabe, T; Asai, H

A synthesis technique of time-domain interconnect models by MIMO type of selective orthogonal least-square method*IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES*

- Leighton, JD; Doherty, S; Elliott, C

Design considerations for high data-rate pre-amplifiers for use in a disk-drive*IEEE TRANSACTIONS ON MAGNETICS*

- Zhang, Q; Liou, JJ; McMacken, J; Thomson, J; Layman, P

Development of robust interconnect model based on design of experiments and multiobjective optimization*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Rogers, JWM; Levenets, V; Pawlowicz, CA; Tarr, NG; Smy, TJ; Plett, C

Post-processed Cu inductors with application to a completely integrated 2-GHz VCO*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Zhang, RT; Roy, K; Koh, CK; Janes, DB

Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Takahashi, S; Edahiro, M; Hayashi, Y

Interconnect design strategy: Structures, repeaters and materials with strategic system performance analysis (S(2)PAL) model*IEEE TRANSACTIONS ON ELECTRON DEVICES*

- Wang, CF; Sahni, S

Matrix multiplication on the OTIS-Mesh optoelectronic computer*IEEE TRANSACTIONS ON COMPUTERS*

- Havemann, RH; Hutchby, JA

High-performance interconnects: An integration overview*PROCEEDINGS OF THE IEEE*

- Banerjee, K; Souri, SJ; Kapur, P; Saraswat, KC

3-D ICs: A novel chip design for improving deep-submicrometer interconnectperformance and systems-on-chip integration*PROCEEDINGS OF THE IEEE*

- Friedman, EG

Clock distribution networks in synchronous digital integrated circuits*PROCEEDINGS OF THE IEEE*

- Kao, WF; Lo, CY; Basel, M; Singh, R

Parasitic extraction: Current state of the art and future trends*PROCEEDINGS OF THE IEEE*

- Ruehli, AE; Cangellaris, AC

Progress in the methodologies for the electrical modeling of interconnectsand electronic packages*PROCEEDINGS OF THE IEEE*

- Chang, MCF; Roychodhury, VP; Zhang, LY; Shin, HC; Qian, YX

RF/wireless interconnect for inter- and intra-chip communications*PROCEEDINGS OF THE IEEE*

- Cong, J

An interconnect-centric design flow for nanometer technologies*PROCEEDINGS OF THE IEEE*

- Caignet, F; Delmas-Bendhia, S; Sicard, E

The challenge of signal integrity in deep-submicrometer CMOS technology*PROCEEDINGS OF THE IEEE*

- Ohmi, T; Sugawa, S; Kotani, K; Hirayama, M; Morimoto, A

New paradigm of silicon technology*PROCEEDINGS OF THE IEEE*

- Restle, PJ; McNamara, TG; Webber, DA; Camporese, PJ; Eng, KF; Jenkins, KA; Allen, DH; Rohn, MJ; Quaranta, MP; Boerstler, DW; Alpert, CJ; Carter, CA; Bailey, RN; Petrovick, JG; Krauter, BL; McCredie, BD

A clock distribution network for microprocessors*IEEE JOURNAL OF SOLID-STATE CIRCUITS*

- Amrutur, BS; Horowitz, MA

Fast low-power decoders for RAMs*IEEE JOURNAL OF SOLID-STATE CIRCUITS*

- Liu, XZ; Wu, ZZ; Cai, H; Yang, YH; Chen, TN; Vallet, CE; Zuhr, RA; Beach, DB; Peng, ZH; Wu, YD; Concolino, TE; Rheingold, AL; Xue, ZL

Reactions of tetrakis(dimethylamide)-titanium, -zirconium and -hafnium with silanes: Synthesis of unusual amide hydride complexes and mechanistic studies of titanium-silicon-nitride (Ti-Si-N) formation*JOURNAL OF THE AMERICAN CHEMICAL SOCIETY*

- Shimizu, T; Natori, K; Sano, N

Transport characteristics of the cross junction of atomic chains*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Morimoto, A; Kotani, K; Sugawa, S; Ohmi, T

Interconnect and substrate structure for gigascale integration*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Lee, W; Cho, H; Cho, B; Yang, HJ; Kim, J; Kim, YS; Jung, WG; Kwon, H; Lee, J; Reucroft, PJ; Lee, C; Lee, E; Lee, J

Thermal stability enhancement of Cu interconnects by employing a self-aligned MgO layer obtained from a Cu(Mg) alloy film*JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS*

- Aoki, Y; Shimada, Y; Iga, K

Evaluation of numerical aperture and focusing characteristics of planar microlens for optical interconnects*JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS*

- Shimada, Y; Aoki, Y; Iga, K

Parallel optical-transmission module using vertical-cavity surface-emitting laser array and micro-optical bench (MOB)*JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS*

- Baldwin, DF; Deshmukh, RD; Hau, CS

Gallium alloy interconnects for flip-chip assembly applications*IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES*

- Dounavis, A; Achar, R; Nakhla, MS

Efficient passive circuit models for distributed networks with frequency-dependent parameters*IEEE TRANSACTIONS ON ADVANCED PACKAGING*

- Eo, Y; Eisenstadt, WR; Shim, J

S-parameter-measurement-based high-speed signal transient characterizationof VLSI interconnects on SiO2-Si substrate*IEEE TRANSACTIONS ON ADVANCED PACKAGING*

- Jiao, C; Cangellaris, AC; Yaghmour, AM; Prince, JL

Sensitivity analysis of multiconductor transmission lines and optimizationfor high-speed interconnect circuit design*IEEE TRANSACTIONS ON ADVANCED PACKAGING*

- Elzinga, M; Virga, KL; Zhao, L; Prince, JL

Pole-residue formulation for transient simulation of high-frequency interconnects using householder LS curve-fitting techniques*IEEE TRANSACTIONS ON ADVANCED PACKAGING*

- Sung, MH; Ryu, W; Kim, H; Kim, J; Kim, J

An efficient crosstalk parameter extraction method for high-speed interconnection lines*IEEE TRANSACTIONS ON ADVANCED PACKAGING*

- Corbett, B; Rodgers, K; Stam, FA; O'Connell, D; Kelly, PV; Crean, GM

Low-stress hybridisation of emitters, detectors and driver circuitry on a silicon motherboard for optoelectronic interconnect architecture*MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING*

- Coosemans, T; Van Hove, A; Bockstaele, R; Vandeputte, K; Vanwassenhove, L; Dhoedt, B; Baets, R; Van Daele, P; Van Koetsem, J

MT (TM)-compatible connectorisation of VCSEL and RCLED arrays to plastic optical fibre ribbon for low cost parallel datalinks*MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING*

- Moreau, V; Renotte, Y; Lion, Y

Planar integration of a polarization-insensitive optical switch with holographic elements*MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING*

- Shen, YL; Guo, YL; Minor, CA

Voiding induced stress redistribution and its reliability implications in metal interconnects*ACTA MATERIALIA*

- Aoki, Y; Shimada, Y; Iga, K

Collimation characteristics of planar microlens for parallel optical interconnect*OPTICAL REVIEW*

- Aoki, Y; Shimada, Y; Mizuno, RJ; Iga, K

Two-dimensional alignment-free optical interconnect using micro optical bench scheme*OPTICAL REVIEW*

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Documento generato il 12/08/20 alle ore 01:26:42