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La ricerca find articoli where soggetti phrase all words 'field programmable gate arrays' sort by level,fasc_key/DESCEND, pagina_ini_num/ASCEND ha restituito 61 riferimenti
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    1. Wilton, SJE; Rose, J; Vranesic, Z
      Structural analysis and generation of synthetic digital circuits with memory

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    2. Cong, L; Wu, XF
      Design and realization of an FPGA-based generator for chaotic frequency hopping sequences

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    3. Taurok, A; Bergauer, H; Padrta, M
      Implementation and synchronisation of the First Level Global Trigger for the CMS experiment at LHC

      NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT
    4. Hien, DS; Senzaki, T
      Development of a fast 12-bit ADC for a nuclear spectroscopy system

      NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT
    5. Annovi, A; Bagliesi, MG; Bardi, A; Carosi, R; Dell'Orso, M; Giannetti, P; Morsani, F; Pietri, M; Varotto, G
      The data organizer: A high traffic node for tracking detector data

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    6. Dauncey, PD; Andress, JC; Adye, TJ; Chevalier, NI; Claxton, BJ; Dyce, N; Foster, B; Galagedera, S; Kurup, A; Mass, A; McFall, JD; McGrath, P; Nash, SJ; Price, DR; Schafer, U; Scott, I; Wallom, DCH
      Design and performance of the level 1 calorimeter trigger for the BABAR detector

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    7. Gollin, GD; Ernst, JA; Williams, JB; Haney, MJ
      The CLEO-III trigger: Analog and digital calorimetry

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    8. Hans, RM; Plager, CL; Selen, MA; Haney, MJ
      The CLEO-III trigger: Axial and stereo tracking

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    9. Selen, MA; Hans, RM; Haney, MJ
      The CLEO-III trigger: Level 1 decision and gating

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    10. Annovi, A; Bagliesi, MG; Bardi, A; Carosi, R; Dell'Orso, M; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G
      The fast tracker processor for hadron collider triggers

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    11. Annovi, A; Bagliesi, MG; Bardi, A; Carosi, R; Dell'Orso, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G
      A pipeline of associative memory boards for track finding

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    12. Dobinson, RW; Haas, S; Korcyl, K; LeVine, MJ; Lokier, J; Martin, B; Meirosu, C; Saka, F; Vella, K
      Testing and modeling Ethernet switches and networks for use in ATLAS high-level triggers

      IEEE TRANSACTIONS ON NUCLEAR SCIENCE
    13. Yang, CH; Chen, SJ; Ho, JM; Tsai, CC
      Efficient routability check algorithms for segmented channel routing

      ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
    14. Figueiredo, MA; Gloster, CS; Stephens, M; Graves, CA; Nakkar, M
      Implementation of multispectral image classification on a remote adaptive computer

      VLSI DESIGN
    15. Henry, MP; Clarke, DW; Archer, N; Bowles, J; Leahy, MJ; Liu, RP; Vignos, J; Zhou, FB
      A self-validating digital Coriolis mass-flow meter: an overview

      CONTROL ENGINEERING PRACTICE
    16. Cong, JSJ; Xu, SJ
      Performance-driven technology mapping for heterogeneous FPGAs

      IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    17. Kavanagh, RC
      Improved digital tachometer with reduced sensitivity to sensor nonideality

      IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
    18. Zhang, XJ; Ng, KW
      A review of high-level synthesis for dynamically reconfigurable FPGAs

      MICROPROCESSORS AND MICROSYSTEMS
    19. Bezerra, EA; Gough, MP
      A guide to migrating from microprocessor to FPGA coping with the support tool limitations

      MICROPROCESSORS AND MICROSYSTEMS
    20. Yip, KW; Ng, TS
      Partial-encryption technique for intellectual property protection of FPGA-based products

      IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
    21. Rogers, S; Scarpino, F; Williamson, T; Lee, MK; Baumbach, J; Cowan, WD; Wiff, DR
      Adaptive optics systems implemented using two-dimensional phase retrieval and a microelectromechanical deformable mirror

      OPTICAL ENGINEERING
    22. Mange, D; Sipper, M; Stauffer, A; Tempesti, G
      Toward robust integrated circuits: The embryonics approach

      PROCEEDINGS OF THE IEEE
    23. Zhang, H; Prabhu, V; George, V; Wan, M; Benes, M; Abnous, A; Rabaey, JM
      Wireless baseband digital signal processing

      IEEE JOURNAL OF SOLID-STATE CIRCUITS
    24. Lloyd, L; Heron, K; Koelmans, AM; Yakovlev, AV
      Asynchronous microprocessors: From high level model to FPGA implementation

      JOURNAL OF SYSTEMS ARCHITECTURE
    25. Yao, X; Higuchi, T
      Promises and challenges of evolvable hardware

      IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART C-APPLICATIONS AND REVIEWS
    26. Chow, P; Seo, SO; Rose, J; Chung, K; Paez-Monzon, G; Rahardja, I
      The design of a SRAM-based field-programmable gate array - Part II: Circuit design and layout

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    27. Chow, P; Seo, SO; Rose, J; Chung, K; Paez-Monzon, G; Rahardja, I
      The design of an SRAM-based field-programmable gate array - Part I: Architecture

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    28. Hauck, S; Li, ZY; Schwabe, E
      Configuration compression for the Xilinx XC6200 FPGA

      IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    29. Benedetti, M; Uicich, G
      New high-performance thyristor gate control set for line-commutated converters

      IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
    30. Purna, KMG; Bhatia, D
      Temporal partitioning and scheduling data flow graphs for reconfigurable computers

      IEEE TRANSACTIONS ON COMPUTERS
    31. ORTEGASANCHEZ C; TYRRELL A
      DESIGN OF A BASIC CELL TO CONSTRUCT EMBRYONIC ARRAYS

      IEE proceedings. Computers and digital techniques
    32. SHNIDMAN NR; MANGIONESMITH WH; POTKONJAK M
      ONLINE FAULT-DETECTION FOR BUS-BASED FIELD-PROGRAMMABLE GATE ARRAYS

      IEEE transactions on very large scale integration (VLSI) systems
    33. MANGE D; SANCHEZ E; STAUFFER A; TEMPESTI G; MARCHAL P; PIGUET C
      EMBRYONICS - A NEW METHODOLOGY FOR DESIGNING FIELD-PROGRAMMABLE GATE ARRAYS WITH SELF-REPAIR AND SELF-REPLICATING PROPERTIES

      IEEE transactions on very large scale integration (VLSI) systems
    34. BETZ V; ROSE J
      EFFECT OF THE PREFABRICATED ROUTING TRACK DISTRIBUTION ON FPGA AREA-EFFICIENCY

      IEEE transactions on very large scale integration (VLSI) systems
    35. TOGAWA N; YANAGISAWA M; OHTSUKI T
      MAPLE-OPT - A PERFORMANCE-ORIENTED SIMULTANEOUS TECHNOLOGY MAPPING, PLACEMENT, AND GLOBAL ROUTING ALGORITHM FOR FPGAS

      IEEE transactions on computer-aided design of integrated circuits and systems
    36. BEETEM J
      REBEL - A CLUSTERING-ALGORITHM FOR LOOK-UP TABLE FPGAS

      IEEE transactions on computer-aided design of integrated circuits and systems
    37. HUTTON MD; ROSE J; GROSSMAN JP; CORNEIL DG
      CHARACTERIZATION AND PARAMETERIZED GENERATION OF SYNTHETIC COMBINATIONAL BENCHMARK CIRCUITS

      IEEE transactions on computer-aided design of integrated circuits and systems
    38. MOORE J; BOTROS NM
      DESIGN AND IMPLEMENTATION OF HOPFIELD NEURAL-NETWORK USING VHDL STRUCTURAL MODELING

      International journal of robotics & automation
    39. MAK WK; WONG DF
      ON OPTIMAL BOARD-LEVEL ROUTING FOR FPGA-BASED LOGIC EMULATION

      IEEE transactions on computer-aided design of integrated circuits and systems
    40. LEE YS; WU ACH
      A PERFORMANCE AND ROUTABILITY-DRIVEN ROUTER FOR FPGAS CONSIDERING PATH DELAYS

      IEEE transactions on computer-aided design of integrated circuits and systems
    41. OLEARY J; BROWN G
      SYNCHRONOUS EMULATION OF ASYNCHRONOUS CIRCUITS

      IEEE transactions on computer-aided design of integrated circuits and systems
    42. JAYARAM R; RAMAN S; RAJ RV; PATNAIK LM
      PETRI NET-BASED MODELING OF A CLASS OF COMPLEX DIGITAL-SYSTEMS

      Computers & electrical engineering
    43. BUCHENRIEDER K; KRESS R; PYTTEL A; SEDLMEIER A; VEITH C
      FPGA-BASED PARALLEL ASIP ARCHITECTURE FOR REACTIVE SYSTEMS

      Electronics Letters
    44. TEMPESTI G; MANGE D; STAUFFER A
      A ROBUST MULTIPLEXER-BASED FPGA INSPIRED BY BIOLOGICAL-SYSTEMS

      Journal of systems architecture
    45. PAYNE R
      ASYNCHRONOUS FPGA ARCHITECTURES

      IEE proceedings. Computers and digital techniques
    46. LU A; DAGLESS E; SAUL J
      TRADEOFF LITERALS AGAINST SUPPORT FOR LOGIC SYNTHESIS OF LUT-BASED FPGAS

      IEE proceedings. Computers and digital techniques
    47. BROWN S; KHELLAH M; LEMIEUX G
      SEGMENTED ROUTING FOR SPEED-PERFORMANCE AND ROUTABILITY IN FIELD-PROGRAMMABLE GATE ARRAYS

      VLSI design
    48. ROY K; GUAN BZ; SECHEN C
      A SEA-OF-GATES STYLE FPGA PLACEMENT ALGORITHM

      VLSI design
    49. BHATIA D; CHOWDHARY A
      A MULTITERMINAL NET ROUTER FOR FIELD-PROGRAMMABLE GATE ARRAYS

      VLSI design
    50. KIM J; PARK MY; SONG YH; BAEK JT
      HIGH-PERFORMANCE ANTIFUSE WITH PLANAR DOUBLE DIELECTRICS ON SI1-XGEX PAD FOR FIELD-PROGRAMMABLE GATE ARRAY APPLICATIONS

      Electronics Letters
    51. KWIAT K; DEBANY W; HARIRI S
      EFFECTS OF TECHNOLOGY MAPPING ON FAULT-DETECTION COVERAGE IN REPROGRAMMABLE FPGAS

      IEE proceedings. Computers and digital techniques
    52. AGARWALA M; BALSARA PT
      AN ARCHITECTURE FOR A DSP FIELD-PROGRAMMABLE GATE ARRAY

      IEEE transactions on very large scale integration (VLSI) systems
    53. HENRY MP
      KEYNOTE PAPER - HARDWARE COMPILATION - A NEW TECHNIQUE FOR RAPID PROTOTYPING OF DIGITAL-SYSTEMS APPLIED TO SENSOR VALIDATION

      Control engineering practice

    54. CRITICAL PATH-ANALYSIS FOR FIELD-PROGRAMMABLE GATE ARRAYS

      Microprocessors and microsystems
    55. CHATTOPADHYAY S; ROY S; CHAUDHURI PP
      KGPMAP - LIBRARY-BASED TECHNOLOGY-MAPPING TECHNIQUE FOR ANTIFUSE BASED FPGAS

      IEE proceedings. Computers and digital techniques
    56. WALKER E; MORGAN G
      PIPELINE RING DATA-FLOW ARCHITECTURE FOR SOLVING LARGE ITERATIVE STRUCTURES

      IEE proceedings. Computers and digital techniques
    57. FARRAHI AH; SARRAFZADEH M
      COMPLEXITY OF THE LOOKUP-TABLE MINIMIZATION PROBLEM FOR FPGA TECHNOLOGY MAPPING

      IEEE transactions on computer-aided design of integrated circuits and systems
    58. FAWCETT BK
      SYSTEM-INTEGRATION FEATURES AND DEVELOPMENT TOOLS KEY TO FPGA DESIGN

      Microprocessors and microsystems
    59. MOHNKE J; MALIK S
      PERMUTATION AND PHASE INDEPENDENT BOOLEAN COMPARISON

      Integration
    60. YORK TA
      SURVEY OF FIELD-PROGRAMMABLE LOGIC DEVICES

      Microprocessors and microsystems
    61. REDINBO GR; NAPOLITANO LM; ANDALEON DD
      MULTIBIT CORRECTING DATA INTERFACE FOR FAULT-TOLERANT SYSTEMS

      I.E.E.E. transactions on computers


ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 06/08/20 alle ore 11:26:59