Catalogo Articoli (Spogli Riviste)

HELP
ATTENZIONE: attualmente gli articoli Current Contents (fonte ISI) a partire dall'anno 2002 sono consultabili sulla Risorsa On-Line

Le informazioni sugli articoli di fonte ISI sono coperte da copyright

La ricerca find articoli where soggetti phrase all words 'design rule' sort by level,fasc_key/DESCEND, pagina_ini_num/ASCEND ha restituito 21 riferimenti
Selezionare un intervallo

Per ulteriori informazioni selezionare i riferimenti di interesse.

    1. Takahashi, T; Sakusabe, T; Shibuya, N; Maeda, H
      Analysis of crosstalk noise on parallel traces with nonequivalent lengths

      ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS
    2. Tang, ZR; Shi, FG
      Effects of preexisting voids on electromigration failure of flip chip solder bumps

      MICROELECTRONICS JOURNAL
    3. Luo, Z; Martonosi, M; Ashar, P
      An edge-endpoint-based configurable hardware architecture for VLSI layout Design Rule Checking

      VLSI DESIGN
    4. Cong, J; Fang, J; Khoo, KY
      Via design rule consideration in multilayer maze routing algorithms

      IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    5. Odanaka, S; Misaka, A; Yamashita, K
      A design hierarchy of IC interconnects and gate patterns

      IEICE TRANSACTIONS ON ELECTRONICS
    6. Pleskacz, WA; Ouyang, CH; Maly, W
      A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits

      IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    7. MOGANTI M; ERCAL F
      A SUBPATTERN LEVEL INSPECTION SYSTEM FOR PRINTED-CIRCUIT BOARDS

      Computer vision and image understanding
    8. JO JH; GERO JS
      SPACE LAYOUT PLANNING USING AN EVOLUTIONARY APPROACH

      Artificial intelligence in engineering
    9. BATORY D; GERACI BJ
      COMPOSITION VALIDATION AND SUBJECTIVITY IN GENVOCA GENERATORS

      IEEE transactions on software engineering
    10. KIM S; SRIDHAR R
      HARDWARE DESIGN RULE CHECKER USING A CAM ARCHITECTURE

      VLSI design
    11. LIETZMANN A; RUDOLPH J; WEISS E
      FAILURE MODES OF PRESSURE-VESSEL COMPONENTS AND THEIR CONSIDERATION IN ANALYSES

      Chemical engineering and processing
    12. KAMOSHIDA M
      TRENDS OF SILICON-WAFER SPECIFICATIONS VS DESIGN RULES IN ULSI DEVICEFABRICATION - PARTICLES, FLATNESS AND IMPURITY DISTRIBUTION DEVIATIONS

      Denki Kagaku Oyobi Kogyo Butsuri Kagaku
    13. YAN PY; LANGSTON J; NEFF J; CHATTERJEE R
      MASK DEFECT PRINTABILITY AND WAFER PROCESS CRITICAL DIMENSION CONTROLAT 0.25 MU-M DESIGN RULES

      JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
    14. SAEKI T; KAKEHASHI E; MORI H; KOGA H; NODA K; FUJITA M; SUGAWARA H; NAGATA K; NISHIMOTO S; MUROTANI T
      DESIGN RULE RELAXATION APPROACH FOR HIGH-DENSITY DRAMS

      IEICE transactions on electronics
    15. WATANABE T; AYUKAWA K; NAKAGOME Y
      3-D-CG MEDIA CHIP - AN EXPERIMENTAL SINGLE-CHIP ARCHITECTURE FOR 3-DIMENSIONAL COMPUTER-GRAPHICS

      IEICE transactions on electronics
    16. MIYASHITA H
      PROCEDURAL DETAILED COMPACTION FOR THE SYMBOLIC LAYOUT DESIGN OF CMOSLEAF-CELLS

      IEICE transactions on fundamentals of electronics, communications and computer science
    17. COTNER C; INUKAI T
      AN ARCHITECTURE DESIGN APPROACH FOR LARGE SATELLITE NETWORKS

      International journal of satellite communications
    18. KAMOSHIDA M
      SILICON-WAFERS FOR 0.25 MU-M TECHNOLOGY AGE - FROM THE VIEWPOINT OF TRENDS OF SILICON DEVICE, PROCESS AND MANUFACTURING ENGINEERING

      Denki Kagaku Oyobi Kogyo Butsuri Kagaku
    19. WATANABE T; AOKI M; KIMURA K; SAKATA T; ITOH K
      THE ADVANTAGES OF A DRAM-BASED DIGITAL ARCHITECTURE FOR LOW-POWER, LARGE-SCALE NEURO-CHIPS

      IEICE transactions on electronics
    20. PHAM CK; SHONO K
      A HARDWARE ACCELERATOR FOR DESIGN-RULE CHECKING IN A BIT-MAPPING CAD-SYSTEM

      IEICE transactions on fundamentals of electronics, communications and computer science
    21. SCHIELE W; KRUGER T; UTESCH MC
      INSERTION OF JOG SERIES IN LAYOUT COMPACTION

      Integration


ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 10/08/20 alle ore 08:36:56