Catalogo Articoli (Spogli Riviste)

HELP
ATTENZIONE: attualmente gli articoli Current Contents (fonte ISI) a partire dall'anno 2002 sono consultabili sulla Risorsa On-Line

Le informazioni sugli articoli di fonte ISI sono coperte da copyright

La ricerca find articoli where soggetti phrase all words 'VLSI ARCHITECTURES' sort by level,fasc_key/DESCEND, pagina_ini_num/ASCEND ha restituito 44 riferimenti
Selezionare un intervallo

Per ulteriori informazioni selezionare i riferimenti di interesse.

    1. Masud, S; McCanny, JV
      Design of silicon IP cores for biorthogonal wavelet transforms

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    2. Fridman, J; Manolakos, ES
      Distributed memory parallel architecture based on modular linear arrays for 2-D separable transforms computation

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    3. Stoica, A; Zebulum, R; Keymeulen, D; Tawel, R; Daud, T; Thakoor, A
      Reconfigurable VLSI architectures for evolvable hardware: From experimental field programmable transistor arrays to evolution-oriented chips

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    4. Mohan, PVA
      Comments on "Breaking the 2n-bit carry-propagation barrier in residue to binary conversion for the [2(n)-1, 2(n), 2(n)+1] moduli set"

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    5. Hamada, N
      Digital signal processing: Progress over the last decade and the challenges ahead

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    6. Eshaghian, MM; Hai, LL
      An optically interconnected reconfigurable mesh

      JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
    7. Yeo, E; Pakzad, P; Nikolic, B; Anantharam, V
      VLSI architectures for iterative decoders in magnetic recording channels

      IEEE TRANSACTIONS ON MAGNETICS
    8. Souani, C; Atri, M; Abid, M; Torki, K; Tourki, R
      Design of new optimized architecture processor for DWT

      REAL-TIME IMAGING
    9. Guo, JH; Wang, CL
      A low-complexity power-sum circuit for GF(2(m)) and its applications

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    10. Hamill, R; McCanny, JV; Walke, RL
      Online CORDIC algorithm and VLSI architecture for implementing QR-array processors

      IEEE TRANSACTIONS ON SIGNAL PROCESSING
    11. Shieh, BJ; Lee, YS; Lee, CY
      A high-throughput memory-based VLC decoder with codeword boundary prediction

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    12. Chakrabarti, C; Lucke, LE
      VLSI architectures for weighted order statistic (WOS) filters

      SIGNAL PROCESSING
    13. Lai, TH; Sheng, MJ
      Sorting on reconfigurable meshes: An irregular decomposition approach

      VLSI DESIGN
    14. Elnaggar, A; Alnuweiri, HM; Ito, MR
      New recursive algorithm for multidimensional convolution

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    15. Lafruit, G; Nachtergaele, L; Bormans, J; Engels, M; Bolsens, I
      Optimal memory organization for scalable texture codecs in MPEG-4

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    16. Lin, R; Olariu, S; Schwing, JL; Wang, BF
      The mesh with hybrid buses: An efficient parallel architecture for digitalgeometry

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    17. Bashagha, AE
      VLSI generalised digit serial architecture for multiplication, division and square root

      SIGNAL PROCESSING
    18. Ramanathan, S; Visvanathan, V; Nandy, SK
      A computational engine for multirate FIR digital filtering

      SIGNAL PROCESSING
    19. Marino, F; Swartzlander, EE
      Parallel implementation of multidimensional transforms without interprocessor communication

      IEEE TRANSACTIONS ON COMPUTERS
    20. CHEN YK; KUNG SY
      A SYSTOLIC DESIGN METHODOLOGY WITH APPLICATION TO FULL-SEARCH BLOCK-MATCHING ARCHITECTURES

      Journal of VLSI signal processing
    21. VERDIER FS; ZAVIDOVIQUE B
      A HIGH-LEVEL SYNTHESIS SYSTEM FOR VLSI IMAGE-PROCESSING APPLICATIONS

      VLSI design (Print)
    22. FUMMI F; SCIUTO D; SILVANO C
      AUTOMATIC-GENERATION OF ERROR CONTROL CODES FOR COMPUTER-APPLICATIONS

      IEEE transactions on very large scale integration (VLSI) systems
    23. AGGOUN A; IBRAHIM MK; ASHUR A
      DESIGN METHODOLOGY FOR SUBDIGIT PIPELINED DIGIT-SERIAL IIR FILTERS

      Signal processing
    24. CHENG HD; WU CY; HUNG DL
      VLSI FOR MOMENT COMPUTATION AND ITS APPLICATION TO BREAST-CANCER DETECTION

      Pattern recognition
    25. HANG HM; CHOU YM; CHENG SC
      MOTION ESTIMATION FOR VIDEO CODING STANDARDS

      Journal of VLSI signal processing systems for signal, image, and video technology
    26. AKOPIAN DA; VAINIO O; AGAIAN SS; ASTOLA JT
      SBNR PROCESSOR FOR STACK FILTERS

      IEEE transactions on circuits and systems. 2, Analog and digital signal processing
    27. CHENG SC; HANG HM
      A COMPARISON OF BLOCK-MATCHING ALGORITHMS MAPPED TO SYSTOLIC-ARRAY IMPLEMENTATION

      IEEE transactions on circuits and systems for video technology
    28. PAN SB; PARK RH
      UNIFIED SYSTOLIC ARRAYS FOR COMPUTATION OF THE DCT DST/DHT/

      IEEE transactions on circuits and systems for video technology
    29. PENG ST; SEDUKHIN I; SEDUKHIN S
      DESIGN OF ARRAY PROCESSORS FOR 2-D DISCRETE FOURIER-TRANSFORM

      IEICE transactions on information and systems
    30. PARHAMI B
      A NOTE ON ARCHITECTURES FOR LARGE-CAPACITY CAMS

      Integration
    31. ASTOLA J; AKOPIAN D; VAINIO O; AGAIAN S
      NEW DIGIT-SERIAL IMPLEMENTATIONS OF STACK FILTERS

      Signal processing
    32. PAN SB; PARK RH
      UNIFIED SYSTOLIC ARRAY FOR FAST COMPUTATION OF THE DISCRETE COSINE TRANSFORM, DISCRETE SINE TRANSFORM, AND DISCRETE HARTLEY TRANSFORM

      Optical engineering
    33. ANTELO E; VILLALBA J; BRUGUERA JD; ZAPATA EL
      HIGH-PERFORMANCE ROTATION ARCHITECTURES BASED ON THE RADIX-4 CORDIC ALGORITHM

      I.E.E.E. transactions on computers
    34. KUHN SA; KLEINER MB; WERNER W
      MULTIPARALLEL SYSTOLIC ARRAYS FOR MULTIDIMENSIONAL FFT-ARCHITECTURES ON 3D-VLSI

      Journal of systems architecture
    35. GRIGORIADIS GK; MERTZIOS BG
      IMPLEMENTATION OF THE VELOCITIES OF THE END-EFFECTOR WITH THE DISTRIBUTED ARITHMETIC ARCHITECTURE

      Journal of intelligent & robotic systems
    36. PARHAMI B
      A NOTE ON DIGITAL-FILTER IMPLEMENTATION USING HYBRID RNS-BINARY ARITHMETIC

      Signal processing
    37. MAZZEO A; VILLANO U
      PARALLEL 1D-FFT COMPUTATION ON CONSTANT-VALENCE MULTICOMPUTERS

      Software, practice & experience
    38. MCQUILLAN SE; MCCANNY JV
      A SYSTEMATIC METHODOLOGY FOR THE DESIGN OF HIGH-PERFORMANCE RECURSIVEDIGITAL-FILTERS

      I.E.E.E. transactions on computers
    39. ESONU MO; ALKHALILI AJ; HARIRI S; ALKHALILI D
      FAULT-TOLERANT DESIGN METHODOLOGY FOR SYSTOLIC ARRAY ARCHITECTURES

      IEE proceedings. Computers and digital techniques
    40. ADAMIDES ED; TSALIDES PG; THANAILAKIS A
      BIT-SERIAL VLSI SORTER WITH HIGH-RELIABILITY SPECIFICATIONS

      Microprocessing and microprogramming
    41. IBRAHIM MK
      NOVEL DIGITAL-FILTER IMPLEMENTATIONS USING HYBRID RNS BINARY ARITHMETIC

      Signal processing
    42. BARSI F; PINOTTI MC
      A FULLY PARALLEL ALGORITHM FOR RESIDUE TO BINARY CONVERSION

      Information processing letters
    43. SUNWOO MH; AGGARWAL JK
      A SLIDING MEMORY PLANE ARRAY PROCESSOR

      IEEE transactions on parallel and distributed systems
    44. DICLAUDIO ED; ORLANDI G; PIAZZA F
      A SYSTOLIC REDUNDANT RESIDUE ARITHMETIC ERROR CORRECTION CIRCUIT

      I.E.E.E. transactions on computers


ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 04/08/20 alle ore 02:28:01