Catalogo Articoli (Spogli Riviste)

HELP
ATTENZIONE: attualmente gli articoli Current Contents (fonte ISI) a partire dall'anno 2002 sono consultabili sulla Risorsa On-Line

Le informazioni sugli articoli di fonte ISI sono coperte da copyright

La ricerca find articoli where soggetti phrase all words 'VLSI' sort by level,fasc_key/DESCEND, pagina_ini_num/ASCEND ha restituito 1582 riferimenti
Si mostrano 100 riferimenti a partire da 1
Selezionare un intervallo

Per ulteriori informazioni selezionare i riferimenti di interesse.

    1. Jeong, GW; Lee, K; Park, S; Park, K
      A branch-and-price algorithm for the Steiner tree packing problem

      COMPUTERS & OPERATIONS RESEARCH
    2. Hanyu, T; Kameyama, M
      Asynchronous current-mode multiple-valued VLSI system based on two-color two-rail coding

      ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS
    3. Murakami, Y; Mikic, BB
      Parametric optimization of multichanneled heat sinks for VLSI chip cooling

      IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES
    4. Pirsch, P; Reuter, C; Wittenburg, JP; Kulaczewski, MB; Stolberg, HJ
      Architecture concepts for multimedia signal processing

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    5. Masud, S; McCanny, JV
      Design of silicon IP cores for biorthogonal wavelet transforms

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    6. Wang, ZF; Suzuki, H; Parhi, KK
      Finite wordlength analysis and adaptive decoding for Turbo/MAP decoders

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    7. Ferretti, M; Rizzo, D
      A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    8. Fridman, J; Manolakos, ES
      Distributed memory parallel architecture based on modular linear arrays for 2-D separable transforms computation

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    9. Hsiao, SF; Tseng, JM
      Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    10. Kwai, DM; Parhami, B
      Scalable linear array architecture with data-driven control for ultrahigh-speed vector quantization

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    11. Gregoretti, F; Passerone, R; Reyneri, LM; Sansoe, C
      A high speed VLSI architecture for handwriting recognition

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    12. Martinez, DR; Moeller, TJ; Teitelbaum, K
      Application of reconfigurable computing to a high performance front-end radar signal processor

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    13. Pillai, RVK; Al-Khalili, D; Al-Khalili, AJ; Shah, SYA
      A low power approach to floating point adder design for DSP applications

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    14. Ghosh, S
      Fundamental principles of modeling timing in hardware description languages

      JOURNAL OF SYSTEMS ARCHITECTURE
    15. Bright, MS; Arslan, T
      Synthesis of low-power DSP systems using a genetic algorithm

      IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION
    16. Chen, RY; Irwin, MJ
      Architecture-level power estimation and design experiments

      ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
    17. Lewis, M; Brackenbury, L
      CADRE: A low-power, low-EMI DSP architecture for digital mobile phones

      VLSI DESIGN
    18. Lin, R
      A regularly structured parallel multiplier with low-power non-binary-logiccounter circuits

      VLSI DESIGN
    19. Cho, GR; Chen, T
      On mixed PTL/static logic for low-power and high-speed circuits

      VLSI DESIGN
    20. Bakalis, D; Kavousianos, X; Vergos, HT; Nikolos, D; Alexiou, GP
      Low power built-in self-test schemes for array and booth multipliers

      VLSI DESIGN
    21. Lee, Y; Choi, J; Moon, G; Kim, J
      Simultaneous switching noise minimization technique using dual layer powerline mutual inductors

      VLSI DESIGN
    22. Choi, JY; Kim, YH; Cho, KR
      Backward propagated capacitance model for register transfer level power estimation

      VLSI DESIGN
    23. Chiou, LY; Muhammand, K; Roy, K
      Signal strength based switching activity modeling and estimation for DSP applications

      VLSI DESIGN
    24. Cho, JD; Cho, JY
      Deep-submicron placement minimizing crosstalk

      VLSI DESIGN
    25. Emmert, JM; Bhatia, DK
      Two-dimensional placement using tabu search

      VLSI DESIGN
    26. Hung, KC; Hung, YS; Huang, YJ
      A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    27. Torbey, E; Knight, JP
      Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    28. Sarwate, DV; Shanbhag, NR
      High-speed architectures for Reed-Solomon decoders

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    29. Jiang, XH; Horiguchi, S
      Statistical skew modeling for general clock distribution networks in presence of process variations

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    30. Chen, ZP; Wei, LQ; Roy, K
      On effective I-DDQ testing of low-voltage CMOS circuits using leakage control techniques

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    31. Cavadini, M; Wosnitza, M; Troster, G
      Multiprocessor system for high-resolution image correlation in real time

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    32. Jin, WJ; Eo, Y; Eisenstadt, WR; Shim, J
      Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    33. Chakraborty, K; Kulkarni, S; Bhattacharya, M; Mazumder, P; Gupta, A
      A physical design tool for built-in self-repairable RAMs

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    34. Olivieri, M
      Design of synchronous and asynchronous variable-latency pipelined multipliers

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    35. Stan, MR
      Low-power CRMOS with subvolt supply voltages

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    36. Leung, OYH; Tsui, CY; Cheng, RSK
      Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    37. Chiricescu, S; Leeser, M; Vai, MM
      Design and analysis of a dynamically reconfigurable three-dimensional FPGA

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    38. Stoica, A; Zebulum, R; Keymeulen, D; Tawel, R; Daud, T; Thakoor, A
      Reconfigurable VLSI architectures for evolvable hardware: From experimental field programmable transistor arrays to evolution-oriented chips

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    39. Djahanshahi, H; Ahmadi, M; Jullien, GA; Miller, WC
      Quantization noise improvement in a hybrid distributed-neuron ANN architecture

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    40. Dinh, AV; Bolton, RJ; Mason, R
      A low latency architecture for computing multiplicative inverses and divisions in GF(2(m))

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    41. Wu, CS; Wu, AY
      Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    42. Alzaher, H; Ismail, M
      A CMOS fully balanced differential difference amplifier and its applications

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    43. Fikos, G; Siskos, S
      Low-voltage low-power accurate CMOS V-T extractor

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    44. Ismail, YI; Friedman, EG; Neves, JL
      Repeater insertion in tree structured inductive interconnect

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    45. Tai, PL; Liu, CT; Wang, JS
      A unified systolic array design for kernel functions of video compression

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    46. Ferri, G; Guerrini, N
      High-valued passive element simulation using low-voltage low-power currentconveyors for fully integrated applications

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    47. Weston, JH; Zhang, CN; Li, H
      Some space considerations of VLSI systolic array mappings

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    48. Cilingiroglu, U; Ozelci, Y
      Multiple-valued static CMOS memory cell

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    49. Mu, F; Svensson, C
      Self-tested self-synchronization circuit for mesochronous clocking

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    50. Tan, BP; Wilson, DM
      Semiparallel rank order filtering in analog VLSI

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    51. Cohen, M; Cauwenberghs, G
      Floating-gate adaptation for focal-plane online nonuniformity correction

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    52. Baldick, R; Kahng, AB; Kennings, A; Markov, IL
      Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    53. Mohan, PVA
      Comments on "Breaking the 2n-bit carry-propagation barrier in residue to binary conversion for the [2(n)-1, 2(n), 2(n)+1] moduli set"

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    54. Moreira, JP; Silva, MM
      Limits to the dynamic range of low-power continuous-time integrators

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    55. Tarim, TB; Ismail, M; Kuntman, HH
      Robust design and yield enhancement of low-voltage CMOS analog integrated circuits

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    56. Parhi, KK
      Approaches to low-power implementations of DSP systems

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    57. Marino, F
      Two fast architectures for the direct 2-D discrete wavelet transform

      IEEE TRANSACTIONS ON SIGNAL PROCESSING
    58. Ma, J; Parhi, KK; Deprettere, EF
      A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms

      IEEE TRANSACTIONS ON SIGNAL PROCESSING
    59. Guo, JI; Li, CC
      A generalized architecture for the one-dimensional discrete cosine and sine transforms

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    60. Wu, PC; Chen, LG
      An efficient architecture for two-dimensional discrete wavelet transform

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    61. Kittitornkun, S; Hu, YH
      Frame-level pipelined motion estimation array processor

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    62. Moshnyaga, VG
      A new computationally adaptive formulation of block-matching motion estimation

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    63. Indiveri, G
      A neuromorphic VLSI device for implementing 2-D selective attention systems

      IEEE TRANSACTIONS ON NEURAL NETWORKS
    64. Parhami, B; Kwai, DM
      A unified formulation of honeycomb and diamond networks

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    65. Tsunekawa, Y; Takahashi, K; Toyoda, S; Miura, M
      High-performance VLSI architecture of multiplierless LMS adaptive filters using distributed arithmetic

      ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE
    66. Shiraishi, S; Haseyama, M; Kitajima, H
      An implementation of a normalized ARMA lattice filter with a CORDIC algorithm

      ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE
    67. Zimmermann, H; Heide, T
      A monolithically integrated 1-Gb/s optical receiver in 1-mu m CMOS technology

      IEEE PHOTONICS TECHNOLOGY LETTERS
    68. Sirakoulis, GC; Karafyllidis, I; Thanailakis, A; Mardiris, V
      A methodology for VLSI implementation of Cellular Automata algorithms using VHDL

      ADVANCES IN ENGINEERING SOFTWARE
    69. Breslin, C; O'Lenskie, A
      Neuromorphic hardware databases for exploring structure-function relationships in the brain

      PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY OF LONDON SERIES B-BIOLOGICAL SCIENCES
    70. Youssef, H; Sait, SM; Adiche, H
      Evolutionary algorithms, simulated annealing and tabu search: a comparative study

      ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE
    71. Etienne-Cummings, R; Gruey, V; Clapp, M
      High performance biomorphic image processing under tight space and power constraints

      AUTONOMOUS ROBOTS
    72. Landolt, O; Mitros, A
      Visual sensor with resolution enhancement by mechanical vibrations

      AUTONOMOUS ROBOTS
    73. Chen, DZ; Xu, JH
      An efficient direct approach for computing shortest rectilinear paths among obstacles in a two-layer interconnection model

      COMPUTATIONAL GEOMETRY-THEORY AND APPLICATIONS
    74. Conti, M; Crippa, P; Orcioni, S; Turchetti, C
      Parametric yield optimization of MOS IC's affected by device mismatch

      ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    75. Indiveri, G
      A current-mode hysteretic winner-take-all network, with excitatory and inhibitory coupling

      ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    76. Tarim, TB; Ismail, M
      Statistical design of the four-MOSFET structure

      ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    77. Ockey, R; Syrzycki, M
      Analysis of manufacturability factors for analog CMOS ADC building blocks

      ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    78. Kwok, CY; Mehrvarz, HR
      Low voltage and mismatch analysis of quadruple source coupled Multi-input Floating-gate Mosfet multiplier with offset trimming

      ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    79. Prasad, MR; Chong, P; Keutzer, K
      Why is combinational ATPG efficiently solvable for practical VLSI circuits?

      JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
    80. Maris, M
      Attention-based navigation in mobile robots using a reconfigurable sensor

      ROBOTICS AND AUTONOMOUS SYSTEMS
    81. Etienne-Cummings, R
      Biologically inspired visual motion detection in VLSI

      INTERNATIONAL JOURNAL OF COMPUTER VISION
    82. Jiang, XH; Horiguchi, S
      Statistical skew modeling and clock period optimization of wafer scale H-tree clock distribution network

      IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
    83. Arima, S; Saito, K
      Operator allocation planning for a product-mix VLSI assembly facility

      IEICE TRANSACTIONS ON ELECTRONICS
    84. Zhang, WJ; Zhou, RD; Ishitani, T; Kasai, R; Kondo, T
      Low-power VLSI architecture for a new block-matching motion estimation algorithm using dual-bit-resolution images

      IEICE TRANSACTIONS ON ELECTRONICS
    85. Ohira, H; Kamemaru, T; Suzuki, H; Asano, K; Yoshimoto, M
      A low power media processor core performable CIF30 fr/s MPEG4/H26x video codec

      IEICE TRANSACTIONS ON ELECTRONICS
    86. Kobayashi, K; Eguchi, M; Iwahashi, T; Shibayama, T; Li, X; Takai, K; Onodera, H
      A low-power high-performance vector-pipeline DSP for low-rate videophones

      IEICE TRANSACTIONS ON ELECTRONICS
    87. Matsubayashi, A
      On the complexity of minimum congestion embedding of acyclic graphs into ladders

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    88. Takagi, N
      A digit-recurrence algorithm for cube rooting

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    89. Honsawek, C; Ito, K; Ohtsuka, T; Adiono, T; Li, DJ; Isshiki, T; Kunieda, H
      System-MSPA design of H.263+video encoder/decoder LSI for videotelephony applications

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    90. Aoki, T; Nakazawa, K; Higuchi, T
      Design of high-radix VLSI dividers without quotient selection tables

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    91. Hamada, N
      Digital signal processing: Progress over the last decade and the challenges ahead

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    92. Goel, AK; Weitemeyer, SE
      Modeling of very high-frequency effects in the interconnection delays on GaAs-based VLSICs

      MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
    93. Ymeri, H; Nauwelaers, B; Maex, K
      Distributed inductance and resistance per-unit-length formulas for VLSI interconnects on silicon substrate

      MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
    94. Ymeri, H; Nauwelaers, B; Maex, K
      On the capacitance and conductance calculations of integrated-circuit interconnects with thick conductors

      MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
    95. Murray, AF
      Novelty detection using products of simple experts - a potential architecture for embedded systems

      NEURAL NETWORKS
    96. van Schaik, A
      Building blocks for electronic spiking neural networks

      NEURAL NETWORKS
    97. Horiuchi, T; Hynna, K
      Spike-based VLSI modeling of the ILD system in the echolocating bat

      NEURAL NETWORKS
    98. Goldberg, DH; Cauwenberghs, G; Andreou, AG
      Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons

      NEURAL NETWORKS
    99. Finvers, IG; Maundy, BJ; Omole, IA; Aronhime, P
      On the design of CMOS current conveyors

      CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE
    100. Puente, V; Izu, C; Beivide, R; Gregorio, JA; Vallejo, F; Prellezo, JM
      The adaptive bubble router

      JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING


ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 19/01/21 alle ore 06:41:39