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1. Jeong, GW; Lee, K; Park, S; Park, K
   A branch-and-price algorithm for the Steiner tree packing problem
   COMPUTERS & OPERATIONS RESEARCH
   
   G.W. Jeong et al., "A branch-and-price algorithm for the Steiner tree packing problem", COMPUT OPER, 29(3), 2002, pp. 221-241
2. Hanyu, T; Kameyama, M
   Asynchronous current-mode multiple-valued VLSI system based on two-color two-rail coding
   ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS
   
   T. Hanyu e M. Kameyama, "Asynchronous current-mode multiple-valued VLSI system based on two-color two-rail coding", ELEC C JP 2, 84(11), 2001, pp. 60-67
3. Murakami, Y; Mikic, BB
   Parametric optimization of multichanneled heat sinks for VLSI chip cooling
   IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES
   
   Y. Murakami e B.B. Mikic, "Parametric optimization of multichanneled heat sinks for VLSI chip cooling", IEEE T COMP, 24(1), 2001, pp. 2-9
4. Pirsch, P; Reuter, C; Wittenburg, JP; Kulaczewski, MB; Stolberg, HJ
   Architecture concepts for multimedia signal processing
   JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
   
   P. Pirsch et al., "Architecture concepts for multimedia signal processing", J VLSI S P, 29(3), 2001, pp. 157-165
5. Masud, S; McCanny, JV
   Design of silicon IP cores for biorthogonal wavelet transforms
   JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
   
   S. Masud e J.V. McCanny, "Design of silicon IP cores for biorthogonal wavelet transforms", J VLSI S P, 29(3), 2001, pp. 179-196
6. Wang, ZF; Suzuki, H; Parhi, KK
   Finite wordlength analysis and adaptive decoding for Turbo/MAP decoders
   JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
   
   Z.F. Wang et al., "Finite wordlength analysis and adaptive decoding for Turbo/MAP decoders", J VLSI S P, 29(3), 2001, pp. 209-221
7. Ferretti, M; Rizzo, D
   A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme
   JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
   
   M. Ferretti e D. Rizzo, "A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme", J VLSI S P, 28(3), 2001, pp. 165-185
8. Fridman, J; Manolakos, ES
   Distributed memory parallel architecture based on modular linear arrays for 2-D separable transforms computation
   JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
   
   J. Fridman e E.S. Manolakos, "Distributed memory parallel architecture based on modular linear arrays for 2-D separable transforms computation", J VLSI S P, 28(3), 2001, pp. 187-203
9. Hsiao, SF; Tseng, JM
   Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec
   JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
   
   S.F. Hsiao e J.M. Tseng, "Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec", J VLSI S P, 28(3), 2001, pp. 205-220
10. Kwai, DM; Parhami, B
    Scalable linear array architecture with data-driven control for ultrahigh-speed vector quantization
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    
    D.M. Kwai e B. Parhami, "Scalable linear array architecture with data-driven control for ultrahigh-speed vector quantization", J VLSI S P, 28(3), 2001, pp. 235-243
11. Gregoretti, F; Passerone, R; Reyneri, LM; Sansoe, C
    A high speed VLSI architecture for handwriting recognition
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    
    F. Gregoretti et al., "A high speed VLSI architecture for handwriting recognition", J VLSI S P, 28(3), 2001, pp. 259-278
12. Martinez, DR; Moeller, TJ; Teitelbaum, K
    Application of reconfigurable computing to a high performance front-end radar signal processor
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    
    D.R. Martinez et al., "Application of reconfigurable computing to a high performance front-end radar signal processor", J VLSI S P, 28(1-2), 2001, pp. 63-83
13. Pillai, RVK; Al-Khalili, D; Al-Khalili, AJ; Shah, SYA
    A low power approach to floating point adder design for DSP applications
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    
    R.V.K. Pillai et al., "A low power approach to floating point adder design for DSP applications", J VLSI S P, 27(3), 2001, pp. 195-213
14. Ghosh, S
    Fundamental principles of modeling timing in hardware description languages
    JOURNAL OF SYSTEMS ARCHITECTURE
    
    S. Ghosh, "Fundamental principles of modeling timing in hardware description languages", J SYST ARCH, 47(5), 2001, pp. 405-426
15. Bright, MS; Arslan, T
    Synthesis of low-power DSP systems using a genetic algorithm
    IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION
    
    M.S. Bright e T. Arslan, "Synthesis of low-power DSP systems using a genetic algorithm", IEEE T EV C, 5(1), 2001, pp. 27-40
16. Chen, RY; Irwin, MJ
    Architecture-level power estimation and design experiments
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
    
    R.Y. Chen e M.J. Irwin, "Architecture-level power estimation and design experiments", ACM T DES A, 6(1), 2001, pp. 50-66
17. Lewis, M; Brackenbury, L
    CADRE: A low-power, low-EMI DSP architecture for digital mobile phones
    VLSI DESIGN
    
    M. Lewis e L. Brackenbury, "CADRE: A low-power, low-EMI DSP architecture for digital mobile phones", VLSI DESIGN, 12(3), 2001, pp. 333-348
18. Lin, R
    A regularly structured parallel multiplier with low-power non-binary-logiccounter circuits
    VLSI DESIGN
    
    R. Lin, "A regularly structured parallel multiplier with low-power non-binary-logiccounter circuits", VLSI DESIGN, 12(3), 2001, pp. 377-390
19. Cho, GR; Chen, T
    On mixed PTL/static logic for low-power and high-speed circuits
    VLSI DESIGN
    
    G.R. Cho e T. Chen, "On mixed PTL/static logic for low-power and high-speed circuits", VLSI DESIGN, 12(3), 2001, pp. 399-406
20. Bakalis, D; Kavousianos, X; Vergos, HT; Nikolos, D; Alexiou, GP
    Low power built-in self-test schemes for array and booth multipliers
    VLSI DESIGN
    
    D. Bakalis et al., "Low power built-in self-test schemes for array and booth multipliers", VLSI DESIGN, 12(3), 2001, pp. 431-448
21. Lee, Y; Choi, J; Moon, G; Kim, J
    Simultaneous switching noise minimization technique using dual layer powerline mutual inductors
    VLSI DESIGN
    
    Y. Lee et al., "Simultaneous switching noise minimization technique using dual layer powerline mutual inductors", VLSI DESIGN, 12(3), 2001, pp. 449-455
22. Choi, JY; Kim, YH; Cho, KR
    Backward propagated capacitance model for register transfer level power estimation
    VLSI DESIGN
    
    J.Y. Choi et al., "Backward propagated capacitance model for register transfer level power estimation", VLSI DESIGN, 12(2), 2001, pp. 221-231
23. Chiou, LY; Muhammand, K; Roy, K
    Signal strength based switching activity modeling and estimation for DSP applications
    VLSI DESIGN
    
    L.Y. Chiou et al., "Signal strength based switching activity modeling and estimation for DSP applications", VLSI DESIGN, 12(2), 2001, pp. 233-243
24. Cho, JD; Cho, JY
    Deep-submicron placement minimizing crosstalk
    VLSI DESIGN
    
    J.D. Cho e J.Y. Cho, "Deep-submicron placement minimizing crosstalk", VLSI DESIGN, 12(1), 2001, pp. 1-12
25. Emmert, JM; Bhatia, DK
    Two-dimensional placement using tabu search
    VLSI DESIGN
    
    J.M. Emmert e D.K. Bhatia, "Two-dimensional placement using tabu search", VLSI DESIGN, 12(1), 2001, pp. 13-23
26. Hung, KC; Hung, YS; Huang, YJ
    A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    K.C. Hung et al., "A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform", IEEE VLSI, 9(5), 2001, pp. 565-576
27. Torbey, E; Knight, JP
    Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    E. Torbey e J.P. Knight, "Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms", IEEE VLSI, 9(5), 2001, pp. 599-607
28. Sarwate, DV; Shanbhag, NR
    High-speed architectures for Reed-Solomon decoders
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    D.V. Sarwate e N.R. Shanbhag, "High-speed architectures for Reed-Solomon decoders", IEEE VLSI, 9(5), 2001, pp. 641-655
29. Jiang, XH; Horiguchi, S
    Statistical skew modeling for general clock distribution networks in presence of process variations
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    X.H. Jiang e S. Horiguchi, "Statistical skew modeling for general clock distribution networks in presence of process variations", IEEE VLSI, 9(5), 2001, pp. 704-717
30. Chen, ZP; Wei, LQ; Roy, K
    On effective I-DDQ testing of low-voltage CMOS circuits using leakage control techniques
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    Z.P. Chen et al., "On effective I-DDQ testing of low-voltage CMOS circuits using leakage control techniques", IEEE VLSI, 9(5), 2001, pp. 718-725
31. Cavadini, M; Wosnitza, M; Troster, G
    Multiprocessor system for high-resolution image correlation in real time
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    M. Cavadini et al., "Multiprocessor system for high-resolution image correlation in real time", IEEE VLSI, 9(3), 2001, pp. 439-449
32. Jin, WJ; Eo, Y; Eisenstadt, WR; Shim, J
    Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    W.J. Jin et al., "Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects", IEEE VLSI, 9(3), 2001, pp. 450-460
33. Chakraborty, K; Kulkarni, S; Bhattacharya, M; Mazumder, P; Gupta, A
    A physical design tool for built-in self-repairable RAMs
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    K. Chakraborty et al., "A physical design tool for built-in self-repairable RAMs", IEEE VLSI, 9(2), 2001, pp. 352-364
34. Olivieri, M
    Design of synchronous and asynchronous variable-latency pipelined multipliers
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    M. Olivieri, "Design of synchronous and asynchronous variable-latency pipelined multipliers", IEEE VLSI, 9(2), 2001, pp. 365-376
35. Stan, MR
    Low-power CRMOS with subvolt supply voltages
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    M.R. Stan, "Low-power CRMOS with subvolt supply voltages", IEEE VLSI, 9(2), 2001, pp. 394-400
36. Leung, OYH; Tsui, CY; Cheng, RSK
    Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    O.Y.H. Leung et al., "Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage", IEEE VLSI, 9(1), 2001, pp. 34-41
37. Chiricescu, S; Leeser, M; Vai, MM
    Design and analysis of a dynamically reconfigurable three-dimensional FPGA
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    S. Chiricescu et al., "Design and analysis of a dynamically reconfigurable three-dimensional FPGA", IEEE VLSI, 9(1), 2001, pp. 186-196
38. Stoica, A; Zebulum, R; Keymeulen, D; Tawel, R; Daud, T; Thakoor, A
    Reconfigurable VLSI architectures for evolvable hardware: From experimental field programmable transistor arrays to evolution-oriented chips
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    
    A. Stoica et al., "Reconfigurable VLSI architectures for evolvable hardware: From experimental field programmable transistor arrays to evolution-oriented chips", IEEE VLSI, 9(1), 2001, pp. 227-232
39. Djahanshahi, H; Ahmadi, M; Jullien, GA; Miller, WC
    Quantization noise improvement in a hybrid distributed-neuron ANN architecture
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    H. Djahanshahi et al., "Quantization noise improvement in a hybrid distributed-neuron ANN architecture", IEEE CIR-II, 48(9), 2001, pp. 842-846
40. Dinh, AV; Bolton, RJ; Mason, R
    A low latency architecture for computing multiplicative inverses and divisions in GF(2(m))
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    A.V. Dinh et al., "A low latency architecture for computing multiplicative inverses and divisions in GF(2(m))", IEEE CIR-II, 48(8), 2001, pp. 789-793
41. Wu, CS; Wu, AY
    Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    C.S. Wu e A.Y. Wu, "Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture", IEEE CIR-II, 48(6), 2001, pp. 548-561
42. Alzaher, H; Ismail, M
    A CMOS fully balanced differential difference amplifier and its applications
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    H. Alzaher e M. Ismail, "A CMOS fully balanced differential difference amplifier and its applications", IEEE CIR-II, 48(6), 2001, pp. 614-620
43. Fikos, G; Siskos, S
    Low-voltage low-power accurate CMOS V-T extractor
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    G. Fikos e S. Siskos, "Low-voltage low-power accurate CMOS V-T extractor", IEEE CIR-II, 48(6), 2001, pp. 626-628
44. Ismail, YI; Friedman, EG; Neves, JL
    Repeater insertion in tree structured inductive interconnect
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    Y.I. Ismail et al., "Repeater insertion in tree structured inductive interconnect", IEEE CIR-II, 48(5), 2001, pp. 471-481
45. Tai, PL; Liu, CT; Wang, JS
    A unified systolic array design for kernel functions of video compression
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    P.L. Tai et al., "A unified systolic array design for kernel functions of video compression", IEEE CIR-II, 48(5), 2001, pp. 523-531
46. Ferri, G; Guerrini, N
    High-valued passive element simulation using low-voltage low-power currentconveyors for fully integrated applications
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    G. Ferri e N. Guerrini, "High-valued passive element simulation using low-voltage low-power currentconveyors for fully integrated applications", IEEE CIR-II, 48(4), 2001, pp. 405-409
47. Weston, JH; Zhang, CN; Li, H
    Some space considerations of VLSI systolic array mappings
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    J.H. Weston et al., "Some space considerations of VLSI systolic array mappings", IEEE CIR-II, 48(4), 2001, pp. 419-424
48. Cilingiroglu, U; Ozelci, Y
    Multiple-valued static CMOS memory cell
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    U. Cilingiroglu e Y. Ozelci, "Multiple-valued static CMOS memory cell", IEEE CIR-II, 48(3), 2001, pp. 282-290
49. Mu, F; Svensson, C
    Self-tested self-synchronization circuit for mesochronous clocking
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    F. Mu e C. Svensson, "Self-tested self-synchronization circuit for mesochronous clocking", IEEE CIR-II, 48(2), 2001, pp. 129-140
50. Tan, BP; Wilson, DM
    Semiparallel rank order filtering in analog VLSI
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    B.P. Tan e D.M. Wilson, "Semiparallel rank order filtering in analog VLSI", IEEE CIR-II, 48(2), 2001, pp. 198-205
51. Cohen, M; Cauwenberghs, G
    Floating-gate adaptation for focal-plane online nonuniformity correction
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    
    M. Cohen e G. Cauwenberghs, "Floating-gate adaptation for focal-plane online nonuniformity correction", IEEE CIR-II, 48(1), 2001, pp. 83-89
52. Baldick, R; Kahng, AB; Kennings, A; Markov, IL
    Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    
    R. Baldick et al., "Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout", IEEE CIRC-I, 48(8), 2001, pp. 947-956
53. Mohan, PVA
    Comments on "Breaking the 2n-bit carry-propagation barrier in residue to binary conversion for the [2(n)-1, 2(n), 2(n)+1] moduli set"
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    
    P.V.A. Mohan, "Comments on "Breaking the 2n-bit carry-propagation barrier in residue to binary conversion for the [2(n)-1, 2(n), 2(n)+1] moduli set"", IEEE CIRC-I, 48(8), 2001, pp. 1031-1031
54. Moreira, JP; Silva, MM
    Limits to the dynamic range of low-power continuous-time integrators
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    
    J.P. Moreira e M.M. Silva, "Limits to the dynamic range of low-power continuous-time integrators", IEEE CIRC-I, 48(7), 2001, pp. 805-817
55. Tarim, TB; Ismail, M; Kuntman, HH
    Robust design and yield enhancement of low-voltage CMOS analog integrated circuits
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    
    T.B. Tarim et al., "Robust design and yield enhancement of low-voltage CMOS analog integrated circuits", IEEE CIRC-I, 48(4), 2001, pp. 475-486
56. Parhi, KK
    Approaches to low-power implementations of DSP systems
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    
    K.K. Parhi, "Approaches to low-power implementations of DSP systems", IEEE CIRC-I, 48(10), 2001, pp. 1214-1224
57. Marino, F
    Two fast architectures for the direct 2-D discrete wavelet transform
    IEEE TRANSACTIONS ON SIGNAL PROCESSING
    
    F. Marino, "Two fast architectures for the direct 2-D discrete wavelet transform", IEEE SIGNAL, 49(6), 2001, pp. 1248-1259
58. Ma, J; Parhi, KK; Deprettere, EF
    A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms
    IEEE TRANSACTIONS ON SIGNAL PROCESSING
    
    J. Ma et al., "A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms", IEEE SIGNAL, 49(2), 2001, pp. 424-437
59. Guo, JI; Li, CC
    A generalized architecture for the one-dimensional discrete cosine and sine transforms
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    
    J.I. Guo e C.C. Li, "A generalized architecture for the one-dimensional discrete cosine and sine transforms", IEEE CIR SV, 11(7), 2001, pp. 874-881
60. Wu, PC; Chen, LG
    An efficient architecture for two-dimensional discrete wavelet transform
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    
    P.C. Wu e L.G. Chen, "An efficient architecture for two-dimensional discrete wavelet transform", IEEE CIR SV, 11(4), 2001, pp. 536-545
61. Kittitornkun, S; Hu, YH
    Frame-level pipelined motion estimation array processor
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    
    S. Kittitornkun e Y.H. Hu, "Frame-level pipelined motion estimation array processor", IEEE CIR SV, 11(2), 2001, pp. 248-251
62. Moshnyaga, VG
    A new computationally adaptive formulation of block-matching motion estimation
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    
    V.G. Moshnyaga, "A new computationally adaptive formulation of block-matching motion estimation", IEEE CIR SV, 11(1), 2001, pp. 118-124
63. Indiveri, G
    A neuromorphic VLSI device for implementing 2-D selective attention systems
    IEEE TRANSACTIONS ON NEURAL NETWORKS
    
    G. Indiveri, "A neuromorphic VLSI device for implementing 2-D selective attention systems", IEEE NEURAL, 12(6), 2001, pp. 1455-1463
64. Parhami, B; Kwai, DM
    A unified formulation of honeycomb and diamond networks
    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    
    B. Parhami e D.M. Kwai, "A unified formulation of honeycomb and diamond networks", IEEE PARALL, 12(1), 2001, pp. 74-80
65. Tsunekawa, Y; Takahashi, K; Toyoda, S; Miura, M
    High-performance VLSI architecture of multiplierless LMS adaptive filters using distributed arithmetic
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE
    
    Y. Tsunekawa et al., "High-performance VLSI architecture of multiplierless LMS adaptive filters using distributed arithmetic", ELEC C JP 3, 84(5), 2001, pp. 1-12
66. Shiraishi, S; Haseyama, M; Kitajima, H
    An implementation of a normalized ARMA lattice filter with a CORDIC algorithm
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE
    
    S. Shiraishi et al., "An implementation of a normalized ARMA lattice filter with a CORDIC algorithm", ELEC C JP 3, 84(4), 2001, pp. 76-86
67. Zimmermann, H; Heide, T
    A monolithically integrated 1-Gb/s optical receiver in 1-mu m CMOS technology
    IEEE PHOTONICS TECHNOLOGY LETTERS
    
    H. Zimmermann e T. Heide, "A monolithically integrated 1-Gb/s optical receiver in 1-mu m CMOS technology", IEEE PHOTON, 13(7), 2001, pp. 711-713
68. Sirakoulis, GC; Karafyllidis, I; Thanailakis, A; Mardiris, V
    A methodology for VLSI implementation of Cellular Automata algorithms using VHDL
    ADVANCES IN ENGINEERING SOFTWARE
    
    G.C. Sirakoulis et al., "A methodology for VLSI implementation of Cellular Automata algorithms using VHDL", ADV EN SOFT, 32(3), 2001, pp. 189-202
69. Breslin, C; O'Lenskie, A
    Neuromorphic hardware databases for exploring structure-function relationships in the brain
    PHILOSOPHICAL TRANSACTIONS OF THE ROYAL SOCIETY OF LONDON SERIES B-BIOLOGICAL SCIENCES
    
    C. Breslin e A. O'Lenskie, "Neuromorphic hardware databases for exploring structure-function relationships in the brain", PHI T ROY B, 356(1412), 2001, pp. 1249-1258
70. Youssef, H; Sait, SM; Adiche, H
    Evolutionary algorithms, simulated annealing and tabu search: a comparative study
    ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE
    
    H. Youssef et al., "Evolutionary algorithms, simulated annealing and tabu search: a comparative study", ENG APP ART, 14(2), 2001, pp. 167-181
71. Etienne-Cummings, R; Gruey, V; Clapp, M
    High performance biomorphic image processing under tight space and power constraints
    AUTONOMOUS ROBOTS
    
    R. Etienne-Cummings et al., "High performance biomorphic image processing under tight space and power constraints", AUTON ROBOT, 11(3), 2001, pp. 227-232
72. Landolt, O; Mitros, A
    Visual sensor with resolution enhancement by mechanical vibrations
    AUTONOMOUS ROBOTS
    
    O. Landolt e A. Mitros, "Visual sensor with resolution enhancement by mechanical vibrations", AUTON ROBOT, 11(3), 2001, pp. 233-239
73. Chen, DZ; Xu, JH
    An efficient direct approach for computing shortest rectilinear paths among obstacles in a two-layer interconnection model
    COMPUTATIONAL GEOMETRY-THEORY AND APPLICATIONS
    
    D.Z. Chen e J.H. Xu, "An efficient direct approach for computing shortest rectilinear paths among obstacles in a two-layer interconnection model", COMP GEOM, 18(3), 2001, pp. 155-166
74. Conti, M; Crippa, P; Orcioni, S; Turchetti, C
    Parametric yield optimization of MOS IC's affected by device mismatch
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    
    M. Conti et al., "Parametric yield optimization of MOS IC's affected by device mismatch", ANALOG IN C, 29(3), 2001, pp. 181-199
75. Indiveri, G
    A current-mode hysteretic winner-take-all network, with excitatory and inhibitory coupling
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    
    G. Indiveri, "A current-mode hysteretic winner-take-all network, with excitatory and inhibitory coupling", ANALOG IN C, 28(3), 2001, pp. 279-291
76. Tarim, TB; Ismail, M
    Statistical design of the four-MOSFET structure
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    
    T.B. Tarim e M. Ismail, "Statistical design of the four-MOSFET structure", ANALOG IN C, 28(1), 2001, pp. 115-121
77. Ockey, R; Syrzycki, M
    Analysis of manufacturability factors for analog CMOS ADC building blocks
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    
    R. Ockey e M. Syrzycki, "Analysis of manufacturability factors for analog CMOS ADC building blocks", ANALOG IN C, 26(3), 2001, pp. 239-255
78. Kwok, CY; Mehrvarz, HR
    Low voltage and mismatch analysis of quadruple source coupled Multi-input Floating-gate Mosfet multiplier with offset trimming
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
    
    C.Y. Kwok e H.R. Mehrvarz, "Low voltage and mismatch analysis of quadruple source coupled Multi-input Floating-gate Mosfet multiplier with offset trimming", ANALOG IN C, 26(2), 2001, pp. 141-156
79. Prasad, MR; Chong, P; Keutzer, K
    Why is combinational ATPG efficiently solvable for practical VLSI circuits?
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
    
    M.R. Prasad et al., "Why is combinational ATPG efficiently solvable for practical VLSI circuits?", J ELEC TEST, 17(6), 2001, pp. 509-527
80. Maris, M
    Attention-based navigation in mobile robots using a reconfigurable sensor
    ROBOTICS AND AUTONOMOUS SYSTEMS
    
    M. Maris, "Attention-based navigation in mobile robots using a reconfigurable sensor", ROBOT AUT S, 34(1), 2001, pp. 53-63
81. Etienne-Cummings, R
    Biologically inspired visual motion detection in VLSI
    INTERNATIONAL JOURNAL OF COMPUTER VISION
    
    R. Etienne-Cummings, "Biologically inspired visual motion detection in VLSI", INT J COM V, 44(3), 2001, pp. 175-198
82. Jiang, XH; Horiguchi, S
    Statistical skew modeling and clock period optimization of wafer scale H-tree clock distribution network
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
    
    X.H. Jiang e S. Horiguchi, "Statistical skew modeling and clock period optimization of wafer scale H-tree clock distribution network", IEICE T INF, E84D(11), 2001, pp. 1476-1485
83. Arima, S; Saito, K
    Operator allocation planning for a product-mix VLSI assembly facility
    IEICE TRANSACTIONS ON ELECTRONICS
    
    S. Arima e K. Saito, "Operator allocation planning for a product-mix VLSI assembly facility", IEICE TR EL, E84C(6), 2001, pp. 832-840
84. Zhang, WJ; Zhou, RD; Ishitani, T; Kasai, R; Kondo, T
    Low-power VLSI architecture for a new block-matching motion estimation algorithm using dual-bit-resolution images
    IEICE TRANSACTIONS ON ELECTRONICS
    
    W.J. Zhang et al., "Low-power VLSI architecture for a new block-matching motion estimation algorithm using dual-bit-resolution images", IEICE TR EL, E84C(3), 2001, pp. 399-409
85. Ohira, H; Kamemaru, T; Suzuki, H; Asano, K; Yoshimoto, M
    A low power media processor core performable CIF30 fr/s MPEG4/H26x video codec
    IEICE TRANSACTIONS ON ELECTRONICS
    
    H. Ohira et al., "A low power media processor core performable CIF30 fr/s MPEG4/H26x video codec", IEICE TR EL, E84C(2), 2001, pp. 157-165
86. Kobayashi, K; Eguchi, M; Iwahashi, T; Shibayama, T; Li, X; Takai, K; Onodera, H
    A low-power high-performance vector-pipeline DSP for low-rate videophones
    IEICE TRANSACTIONS ON ELECTRONICS
    
    K. Kobayashi et al., "A low-power high-performance vector-pipeline DSP for low-rate videophones", IEICE TR EL, E84C(2), 2001, pp. 193-201
87. Matsubayashi, A
    On the complexity of minimum congestion embedding of acyclic graphs into ladders
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    
    A. Matsubayashi, "On the complexity of minimum congestion embedding of acyclic graphs into ladders", IEICE T FUN, E84A(5), 2001, pp. 1218-1226
88. Takagi, N
    A digit-recurrence algorithm for cube rooting
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    
    N. Takagi, "A digit-recurrence algorithm for cube rooting", IEICE T FUN, E84A(5), 2001, pp. 1309-1314
89. Honsawek, C; Ito, K; Ohtsuka, T; Adiono, T; Li, DJ; Isshiki, T; Kunieda, H
    System-MSPA design of H.263+video encoder/decoder LSI for videotelephony applications
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    
    C. Honsawek et al., "System-MSPA design of H.263+video encoder/decoder LSI for videotelephony applications", IEICE T FUN, E84A(11), 2001, pp. 2614-2622
90. Aoki, T; Nakazawa, K; Higuchi, T
    Design of high-radix VLSI dividers without quotient selection tables
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    
    T. Aoki et al., "Design of high-radix VLSI dividers without quotient selection tables", IEICE T FUN, E84A(11), 2001, pp. 2623-2631
91. Hamada, N
    Digital signal processing: Progress over the last decade and the challenges ahead
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    
    N. Hamada, "Digital signal processing: Progress over the last decade and the challenges ahead", IEICE T FUN, E84A(1), 2001, pp. 80-90
92. Goel, AK; Weitemeyer, SE
    Modeling of very high-frequency effects in the interconnection delays on GaAs-based VLSICs
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
    
    A.K. Goel e S.E. Weitemeyer, "Modeling of very high-frequency effects in the interconnection delays on GaAs-based VLSICs", MICROW OPT, 31(3), 2001, pp. 229-233
93. Ymeri, H; Nauwelaers, B; Maex, K
    Distributed inductance and resistance per-unit-length formulas for VLSI interconnects on silicon substrate
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
    
    H. Ymeri et al., "Distributed inductance and resistance per-unit-length formulas for VLSI interconnects on silicon substrate", MICROW OPT, 30(5), 2001, pp. 302-304
94. Ymeri, H; Nauwelaers, B; Maex, K
    On the capacitance and conductance calculations of integrated-circuit interconnects with thick conductors
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
    
    H. Ymeri et al., "On the capacitance and conductance calculations of integrated-circuit interconnects with thick conductors", MICROW OPT, 30(5), 2001, pp. 335-339
95. Murray, AF
    Novelty detection using products of simple experts - a potential architecture for embedded systems
    NEURAL NETWORKS
    
    A.F. Murray, "Novelty detection using products of simple experts - a potential architecture for embedded systems", NEURAL NETW, 14(9), 2001, pp. 1257-1264
96. van Schaik, A
    Building blocks for electronic spiking neural networks
    NEURAL NETWORKS
    
    A. van Schaik, "Building blocks for electronic spiking neural networks", NEURAL NETW, 14(6-7), 2001, pp. 617-628
97. Horiuchi, T; Hynna, K
    Spike-based VLSI modeling of the ILD system in the echolocating bat
    NEURAL NETWORKS
    
    T. Horiuchi e K. Hynna, "Spike-based VLSI modeling of the ILD system in the echolocating bat", NEURAL NETW, 14(6-7), 2001, pp. 755-762
98. Goldberg, DH; Cauwenberghs, G; Andreou, AG
    Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons
    NEURAL NETWORKS
    
    D.H. Goldberg et al., "Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons", NEURAL NETW, 14(6-7), 2001, pp. 781-793
99. Finvers, IG; Maundy, BJ; Omole, IA; Aronhime, P
    On the design of CMOS current conveyors
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE
    
    I.G. Finvers et al., "On the design of CMOS current conveyors", CAN J EL C, 26(1), 2001, pp. 35-40
100. Puente, V; Izu, C; Beivide, R; Gregorio, JA; Vallejo, F; Prellezo, JM
     The adaptive bubble router
     JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
     
     V. Puente et al., "The adaptive bubble router", J PAR DISTR, 61(9), 2001, pp. 1180-1208