Catalogo Articoli (Spogli Riviste)

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La ricerca find articoli where soggetti phrase all words 'PROCESSOR ARRAY' sort by level,fasc_key/DESCEND, pagina_ini_num/ASCEND ha restituito 100 riferimenti
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    1. Gregoretti, F; Passerone, R; Reyneri, LM; Sansoe, C
      A high speed VLSI architecture for handwriting recognition

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    2. Pan, Y; Zheng, SQ; Li, KQ; Shen, H
      An improved generalization of mesh-connected computers with multiple buses

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    3. Parhami, B; Kwai, DM
      A unified formulation of honeycomb and diamond networks

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    4. Fimmel, D; Merker, R
      Design of processor arrays for reconfigurable architectures

      JOURNAL OF SUPERCOMPUTING
    5. Takanami, I
      A graph-theoretic approach to minimizing the number of dangerous processors in fault-tolerant mesh-connected processor arrays

      IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
    6. Qian, F; Li, GQ; Alam, MS
      Optoelectronic quotient-selected modified signed-digit division

      OPTICAL ENGINEERING
    7. Youn, HY; Oh, CG; Choo, H; Chung, JW; Lee, D
      An efficient algorithm-based fault tolerance design using the weighted data-check relationship

      IEEE TRANSACTIONS ON COMPUTERS
    8. Liu, GP; Lee, KY; Jordan, HF
      n-Dimensional processor arrays with optical dBuses

      JOURNAL OF SUPERCOMPUTING
    9. Cam, H
      List ranking on processor arrays

      JOURNAL OF SYSTEMS AND SOFTWARE
    10. Ferrari, A; Borgatti, M; Guerrieri, R
      A complete system for NN classification based on a VLSI array processor

      PATTERN RECOGNITION
    11. Gusev, M; Evans, DJ
      Algorithm transformations for the data broadcast elimination method

      INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS
    12. Tsuda, N
      Fault-tolerant processor arrays using additional bypass linking allocated by graph-node coloring

      IEEE TRANSACTIONS ON COMPUTERS
    13. Pan, Y; Li, KQ; Hamdi, M
      An improved constant-time algorithm for computing the Radon and Hough transforms on a reconfigurable mesh

      IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART A-SYSTEMS AND HUMANS
    14. Li, DJ; Jiang, L; Isshiki, T; Kunieda, H
      New VLSI array processor design for image window operations

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    15. Kontoghiorghes, EJ
      Ordinary linear model estimation on a massively parallel SIMD computer

      CONCURRENCY-PRACTICE AND EXPERIENCE
    16. Miyamori, T; Olukotun, K
      REMARC: Reconfigurable multimedia array coprocessor

      IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
    17. Li, DJ; Jiang, L; Kunieda, H
      Design optimization of VLSI array processor architecture for window image processing

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    18. Li, KQ; Pan, Y; Zheng, SQ
      Parallel matrix computations using a reconfigurable pipelined optical bus

      JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
    19. Kuo, CJ; Hsu, CC; Fang, WC
      Parallel directed graph algorithms on directional processor arrays with reconfigurable bus systems

      NEW GENERATION COMPUTING
    20. Fernando, JA; Jean, JSN
      Processor array design with FPGA area constraint

      IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    21. Ramanathan, S; Visvanathan, V
      Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

      INTEGRATION-THE VLSI JOURNAL
    22. Clementi, E; Corongiu, G
      Early parallelism with a loosely coupled array of processors: The ICAP experiment

      PARALLEL COMPUTING
    23. Zhu, YS; Zhou, H; Gu, H; Wang, ZZ
      Fixed-point error analysis and an efficient array processor design of two-dimensional sliding DFT

      SIGNAL PROCESSING
    24. Siyal, MY; Fathy, M
      A programmable image processor for real-time image processing applications

      MICROPROCESSORS AND MICROSYSTEMS
    25. Li, GQ; Qian, F; Ruan, H; Liu, L
      Parallel optical negabinary signed-digit computing: algorithm and optical implementation

      OPTICAL ENGINEERING
    26. Yamada, M; Fukuzawa, M; Kitsunezuka, Y
      One-dimensional processor array system for fast analysis of tissue motion in ultrasonogram

      JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS
    27. KIM GY; BAEK Y; LEE HK
      DATA DISTRIBUTION AND ALIGNMENT SCHEME FOR CONFLICT-FREE MEMORY ACCESS IN PARALLEL IMAGE-PROCESSING SYSTEM

      IEICE transactions on information and systems
    28. SHIGEI N; MIYAJIMA H
      ON THE SEARCH FOR EFFECTIVE SPARE ARRANGEMENT OF RECONFIGURABLE PROCESSOR ARRAYS USING GENETIC ALGORITHM

      IEICE transactions on fundamentals of electronics, communications and computer science
    29. GRAMMATIKAKIS MD; HSU DF; KRAETZL M; SIBEYN JF
      PACKET ROUTING IN FIXED-CONNECTION NETWORKS - A SURVEY

      Journal of parallel and distributed computing (Print)
    30. KIM SY; CHWA KY
      MULTIPLE GRAPH EMBEDDINGS INTO A PROCESSOR ARRAY WITH SPANNING BUSES

      Journal of parallel and distributed computing (Print)
    31. Ong, S; Sunwoo, MH
      Implementation of a sliding memory plane image processor

      JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
    32. KIM JM; KIM Y; KIM SD; HAN TD; YANG SB
      AN ADAPTIVE PARALLEL COMPUTER VISION SYSTEM

      International journal of pattern recognition and artificial intelligence
    33. ROCCATANO D; BIZZARRI R; CHILLEMI G; SANNA N; DINOLA A
      DEVELOPMENT OF A PARALLEL MOLECULAR-DYNAMICS CODE ON SIMD COMPUTERS -ALGORITHM FOR USE OF PAIR LIST CRITERION

      Journal of computational chemistry
    34. RUAN H; CHENG SC; GAN FX
      PARALLEL OPTICAL LOGIC PROCESSOR AND BIT SLICE-FULL ADDER USING A SINGLE-ELECTRON TRAPPING DEVICE

      Optics and Laser Technology
    35. Kwai, DM; Parhami, B
      Pruned three-dimensional toroidal networks

      INFORMATION PROCESSING LETTERS
    36. OTT P; BADER G
      2 DIRECTIONS IN PARALLEL OPTICAL-IMAGE PREPROCESSING DEMONSTRATED ON THE HOUGH TRANSFORM

      AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
    37. GANAPATHY KN; WAH BW; LI CW
      DESIGNING A SCALABLE PROCESSOR ARRAY FOR RECURRENT COMPUTATIONS

      IEEE transactions on parallel and distributed systems
    38. LI KQ
      CONSTANT-TIME BOOLEAN MATRIX MULTIPLICATION ON A LINEAR-ARRAY WITH A RECONFIGURABLE PIPELINED BUS SYSTEM

      Journal of supercomputing
    39. SHIGEI N; MIYAJIMA H; MURASHIMA S
      ON EFFICIENT SPARE ARRANGEMENTS AND AN ALGORITHM WITH RELOCATING SPARES FOR RECONFIGURING PROCESSOR ARRAYS

      IEICE transactions on fundamentals of electronics, communications and computer science
    40. OZAWA T; YAMAGUCHI T
      SPARE ALLOCATION AND COMPENSATION-PATH FINDING FOR RECONFIGURING WSI PROCESSOR ARRAYS HAVING SINGLE-TRACK SWITCHES

      IEICE transactions on fundamentals of electronics, communications and computer science
    41. TAHIR JM; DLAY SS; GORGUINAGUIB RN; HINTON OR
      CONCURRENT ERROR-DETECTION IN FAST FERMAT NUMBER TRANSFORM NETWORKS

      Computer systems science and engineering
    42. CHLEBUS BS
      MESH SORTING AND SELECTION OPTIMAL ON THE AVERAGE

      Computers and artificial intelligence
    43. KAUFMANN M; RAMAN R; SIBEYN JF
      ROUTING ON MESHES WITH BUSES

      Algorithmica
    44. OVERILL RE; WILSON S
      DATA-PARALLEL EVALUATION OF UNIVARIATE POLYNOMIALS BY THE KNUTH-EVE ALGORITHM

      Parallel computing
    45. FITZPATRICK S; HARMER TJ; STEWART A; CLINT M; BOYLE JM
      THE AUTOMATED TRANSFORMATION OF ABSTRACT SPECIFICATIONS OF NUMERICAL ALGORITHMS INTO EFFICIENT ARRAY PROCESSOR IMPLEMENTATIONS

      Science of computer programming
    46. KWAI DM; PARHAMI B
      AN ONLINE FAULT-DIAGNOSIS SCHEME FOR LINEAR PROCESSOR ARRAYS

      Microprocessors and microsystems
    47. AMOR M; LOPEZ J; ARGUELLO F; ZAPATA EL
      MAPPING TRIDIAGONAL SYSTEM ALGORITHMS ONTO MESH-CONNECTED COMPUTERS

      International journal of high speed computing
    48. LI YM; PAN Y; ZHENG SQ
      PIPELINED TIME-DIVISION MULTIPLEXING OPTICAL BUS WITH CONDITIONAL DELAYS

      Optical engineering
    49. MACFARLANE A; ROBERTSON SE; MCCANN JA
      PARALLEL COMPUTING IN INFORMATION-RETRIEVAL - AN UPDATED REVIEW

      Journal of Documentation
    50. EVANS DJ; GUSEV M
      ALGORITHM TRANSFORMATIONS FOR COMPUTATIONAL AND DATA BROADCAST

      International journal of computer mathematics
    51. CHEN YY; UPADHYAYA SJ; CHENG CH
      A COMPREHENSIVE RECONFIGURATION SCHEME FOR FAULT-TOLERANT VLSI WSI ARRAY PROCESSORS/

      I.E.E.E. transactions on computers
    52. VESELOVSKII GG; KUPRIYANOVA MV
      ANALYSIS OF SOME COMBINATORIAL PROPERTIES OF A BINARY HYPERCUBE

      Automation and remote control
    53. RUOCCO AS; FRIEDER O
      CLUSTERING AND CLASSIFICATION OF LARGE DOCUMENT BASES IN A PARALLEL ENVIRONMENT

      Journal of the American Society for Information Science
    54. ROBIN F; RENAUDIN M; PRIVAT G; VANDENBOSSCHE N
      FUNCTIONALLY ASYNCHRONOUS ARRAY PROCESSOR FOR MORPHOLOGICAL FILTERINGOF GREYSCALE IMAGES

      IEE proceedings. Computers and digital techniques
    55. YOUN HY; LEE JY
      AN EFFICIENT DICTIONARY MACHINE USING HEXAGONAL PROCESSOR ARRAYS

      IEEE transactions on parallel and distributed systems
    56. COLBROOK A; BREWER EA; DELLAROCAS CN; WEIHL WE
      ALGORITHMS FOR SEARCH-TREES ON MESSAGE-PASSING ARCHITECTURES

      IEEE transactions on parallel and distributed systems
    57. BOURBAKIS NG; MERTOGUNO JS
      KYDON - AN AUTONOMOUS, MULTILAYER IMAGE-UNDERSTANDING SYSTEM - LOWER LAYERS

      Engineering applications of artificial intelligence
    58. SHIGEI N; MIYAJIMA H; ISHIZAKA T; MURASHIMA S
      ON METHODS FOR RECONFIGURING PROCESSOR ARRAYS

      IEICE transactions on information and systems
    59. MIYASHITA K; TSUJINO Y; TOKURA N
      A COMPARISON BETWEEN THE COMPUTATIONAL POWER OF PARBS AND RMBM

      IEICE transactions on information and systems
    60. KANEKO M; MIYAUCHI H
      A SYSTEMATIC DESIGN OF FAULT-TOLERANT SYSTOLIC ARRAYS BASED ON TRIPLEMODULAR-REDUNDANCY IN TIME-PROCESSOR SPACE

      IEICE transactions on information and systems
    61. LI DJ; KUNIEDA H
      MEMORY SHARING PROCESSOR ARRAY (MSPA) ARCHITECTURE

      IEICE transactions on fundamentals of electronics, communications and computer science
    62. LI DJ; KUNIEDA H
      AUTOMATIC SYNTHESIS OF A SERIAL INPUT MULTIPROCESSOR ARRAY

      IEICE transactions on fundamentals of electronics, communications and computer science
    63. TRAHAN JL; VAIDYANATHAN R; THIRUCHELVAN RK
      ON THE POWER OF SEGMENTING AND FUSING BUSES

      Journal of parallel and distributed computing
    64. CHEUNG S; LAU FCM
      ROUTING WITH LOCALITY ON MESHES WITH BUSES

      Journal of parallel and distributed computing
    65. ARGUELLO F; AMOR M; ZAPATA EL
      FFTS ON MESH-CONNECTED COMPUTERS

      Parallel computing
    66. WEN Z; YANG X; ZHOU S; YEH P; LIU HK
      A MULTICHANNEL OPTICAL PROCESSOR COMBINING SPACE, POLARIZATION AND WAVELENGTH MULTIPLEXING

      Optik
    67. CHEN PP; MOURAD AN; FUCHS WK
      PROBABILITY OF CORRECTNESS OF PROCESSOR-ARRAY OUTPUTS USING PERIODIC CONCURRENT ERROR-DETECTION

      IEEE transactions on reliability
    68. CHUNG KL; LIN HY
      HOUGH TRANSFORM ON RECONFIGURABLE MESHES

      Computer vision and image understanding
    69. VEHLIES U
      STEPWISE TRANSFORMATION OF ALGORITHMS INTO ARRAY PROCESSOR ARCHITECTURES BY THE DECOMP

      VLSI design
    70. SEZNEC A; LENFANT J
      ODD MEMORY-SYSTEMS - A NEW APPROACH

      Journal of parallel and distributed computing
    71. JANG J; PRASANNA VK
      AN OPTIMAL SORTING ALGORITHM ON RECONFIGURABLE MESH

      Journal of parallel and distributed computing
    72. NAKANO K
      OPTIMAL INITIALIZING ALGORITHMS FOR A RECONFIGURABLE MESH

      Journal of parallel and distributed computing
    73. ASENOV A; REID D; BARKER JR
      SPEED-UP OF SCALABLE ITERATIVE LINEAR SOLVERS IMPLEMENTED ON AN ARRAYOF TRANSPUTERS

      Parallel computing
    74. TANNO K; TAKETA T; HORIGUCHI S
      PARALLEL FFT ALGORITHMS USING RADIX-4 BUTTERFLY COMPUTATION ON AN 8-NEIGHBOR PROCESSOR ARRAY

      Parallel computing
    75. JANG JW; PARK H; PRASANNA VK
      A FAST ALGORITHM FOR COMPUTING A HISTOGRAM ON RECONFIGURABLE MESH

      IEEE transactions on pattern analysis and machine intelligence
    76. LIN CF; HORNG SJ; KAO TW
      GENERALIZED ROTATE SORT ON MESH-CONNECTED COMPUTERS WITH MULTIPLE BROADCASTING USING FEWER PROCESSORS

      International journal of high speed computing
    77. SHI HC; RITTER GX; WILSON JN
      SIMULATIONS BETWEEN 2 RECONFIGURABLE MESH MODELS

      Information processing letters
    78. ZAROWSKI CJ
      PARALLEL IMPLEMENTATION OF THE SCHUR BERLEKAMP-MASSEY ALGORITHM ON A LINEARLY CONNECTED PROCESSOR ARRAY

      I.E.E.E. transactions on computers
    79. GLINSKI S; ROE D
      SPOKEN LANGUAGE RECOGNITION ON A DSP ARRAY PROCESSOR

      IEEE transactions on parallel and distributed systems
    80. MOONEN M
      IMPLEMENTING THE SQUARE-ROOT INFORMATION KALMAN FILTER ON A JACOBI-TYPE SYSTOLIC ARRAY

      Journal of VLSI signal processing
    81. MOONEN M; VANDEWALLE J
      A JACOBI-TYPE SYSTOLIC ALGORITHM FOR RICCATI AND LYAPUNOV EQUATIONS

      Journal of parallel and distributed computing
    82. ALNUWEIRI HM; PRASANNA VK
      EFFICIENT PARALLEL COMPUTATIONS ON THE REDUCED MESH OF TREES ORGANIZATION

      Journal of parallel and distributed computing
    83. LEUNG JYT; SHENDE SM
      ON MULTIDIMENSIONAL PACKET ROUTING FOR MESHES WITH BUSES

      Journal of parallel and distributed computing
    84. LIN SS
      CONSTANT-TIME ALGORITHMS FOR THE CHANNEL ASSIGNMENT PROBLEM ON PROCESSOR ARRAYS WITH RECONFIGURABLE BUS SYSTEMS

      IEEE transactions on computer-aided design of integrated circuits and systems
    85. ASENOV A; REID D; BARKER JR
      SPEED-UP OF SCALABLE ITERATIVE LINEAR SOLVERS IMPLEMENTED ON AN ARRAYOF TRANSPUTERS

      Parallel computing
    86. NIKOLAIDIS SS; THEODORIDIS S; GOUTIS CE
      ARRAY PROCESSOR FOR BLOCK ADAPTIVE LS FIR FILTERING

      Signal processing
    87. PRADEEP B; MURTHY CSR
      PARALLEL RECOGNITION AND PARSING ON MESH-CONNECTED COMPUTERS WITH MULTIPLE BROADCASTING

      Computer languages
    88. CHEN YC; CHEN WT
      CONSTANT-TIME SORTING ON RECONFIGURABLE MESHES

      I.E.E.E. transactions on computers
    89. KITTICHAIKOONKIT S; KAMEYAMA M
      A MINIMUM-LATENCY LINEAR-ARRAY FFT PROCESSOR FOR ROBOTICS

      IEICE transactions on information and systems
    90. AJIRO M; MIYATA H; KAN T; SOGA M; ONO M
      SATELLITE IMAGE-PROCESSING SYSTEM UTILIZING AN EXTENDED CELLULAR ARRAY PROCESSOR

      IEICE transactions on information and systems
    91. TAMARU K
      THE TREND OF FUNCTIONAL MEMORY DEVELOPMENT

      IEICE transactions on electronics
    92. TAKAHASHI J
      A HARDWARE ARCHITECTURE DESIGN METHODOLOGY FOR HIDDEN MARKOV MODEL-BASED RECOGNITION SYSTEMS USING PARALLEL-PROCESSING

      IEICE transactions on fundamentals of electronics, communications and computer science
    93. NAKANO K
      OPTIMAL SORTING ALGORITHMS ON BUS-CONNECTED PROCESSOR ARRAYS

      IEICE transactions on fundamentals of electronics, communications and computer science
    94. OLARIU S; SCHWING JL; ZHANG JY
      FAST COMPONENT LABELING AND CONVEX-HULL COMPUTATION ON RECONFIGURABLEMESHES

      Image and vision computing
    95. MANTHARAM M; EBERLEIN PJ
      NEW JACOBI-SETS FOR PARALLEL COMPUTATIONS

      Parallel computing
    96. JOHNSSON SL
      MINIMIZING THE COMMUNICATION TIME FOR MATRIX MULTIPLICATION ON MULTIPROCESSORS

      Parallel computing
    97. VAIDYANATHAN R; TRAHAN JL
      OPTIMAL SIMULATION OF MULTIDIMENSIONAL RECONFIGURABLE MESHES BY 2-DIMENSIONAL RECONFIGURABLE MESHES

      Information processing letters
    98. LOPEZBENITEZ N; TRIVEDI KS
      MULTIPROCESSOR PERFORMABILITY ANALYSIS

      IEEE transactions on reliability
    99. HUGHEY R
      CONCURRENT ERROR-DETECTION ON PROGRAMMABLE SYSTOLIC ARRAYS

      I.E.E.E. transactions on computers
    100. KIM JH; RHEE PK
      THE RULE-BASED APPROACH TO RECONFIGURATION OF 2-D PROCESSOR ARRAYS

      I.E.E.E. transactions on computers


ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 26/01/21 alle ore 14:47:06