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La ricerca find articoli where soggetti phrase all words 'PROCESSOR' sort by level,fasc_key/DESCEND, pagina_ini_num/ASCEND ha restituito 1273 riferimenti
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    1. Boutalis, YS; Tsirikolias, K; Metrtzios, BG; Andreadis, IT
      Implementation of morphological filters using coordinate logic operations

      PATTERN RECOGNITION
    2. Michael, CW; McConnel, J; Pecott, J; Afify, AM; Al-Khafaji, B
      Comparison of ThinPrep and TriPath PREP liquid-based preparations in nongynecologic specimens: A pilot study

      DIAGNOSTIC CYTOPATHOLOGY
    3. Cochand-Priollet, B; Le Gales, C; de Cremoux, P; Molinie, V; Sastre-Garau, X; Vacher-Lavenu, MC; Vielh, P; Coste, J
      Cost-effectiveness of monolayers and human papillomavirus testing comparedto that of conventional Papanicolaou smears for cervical cancer screening:Protocol of the study of the French Society of Clinical Cytology

      DIAGNOSTIC CYTOPATHOLOGY
    4. Nasuti, JF; Tam, D; Gupta, PK
      Diagnostic value of liquid-based (ThinPrep (R)) preparations in nongynecologic cases

      DIAGNOSTIC CYTOPATHOLOGY
    5. Yue, KK; Lilja, DJ
      Implementing a dynamic processor allocation policy for multiprogrammed parallel applications in the Solaris (TM) operating system

      CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE
    6. Pfingst, BE; Franck, KH; Xu, L; Bauer, EM; Zwolan, TA
      Effects of electrode configuration and place of stimulation on speech perception with cochlear prostheses

      JARO
    7. Kienle, HM
      Using smgn for rapid protoptyping of small domain-specific languages

      ACM SIGPLAN NOTICES
    8. Kessler, C; Bednarski, A
      A dynamic programming approach to optimal integrated code generation

      ACM SIGPLAN NOTICES
    9. Schnarr, EC; Hill, MD; Larus, JR
      Facile: A language and compiler for high-performance processor simulators

      ACM SIGPLAN NOTICES
    10. Kwai, DM; Parhami, B
      Scalable linear array architecture with data-driven control for ultrahigh-speed vector quantization

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    11. Gregoretti, F; Passerone, R; Reyneri, LM; Sansoe, C
      A high speed VLSI architecture for handwriting recognition

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    12. Wan, M; Zhang, H; George, V; Benes, M; Abnous, A; Prabhu, V; Rabaey, J
      Design methodology of a low-energy reconfigurable single-chip DSP system

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    13. Martinez, DR; Moeller, TJ; Teitelbaum, K
      Application of reconfigurable computing to a high performance front-end radar signal processor

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    14. Kang, JY; Lee, J; Sung, WY
      A compiler-friendly RISC-based digital signal processor synthesis and performance evaluation

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    15. Lee, C; Kin, J; Potkonjak, M; Mangione-Smith, WH
      Exploring hypermedia processor design space

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    16. Harwood, A; Shen, H
      Using fundamental electrical theory for varying time quantum uni-processorscheduling

      JOURNAL OF SYSTEMS ARCHITECTURE
    17. Shimonishi, H; Murase, T
      A network processor architecture for very high speed line interfaces

      JOURNAL OF COMMUNICATIONS AND NETWORKS
    18. Jun, DS; Choe, J; Leon-Garcia, A
      Credit-based processor sharing for decoupled delay and bandwidth allocation

      IEEE COMMUNICATIONS LETTERS
    19. Van Praet, J; Lanneer, D; Geurts, W; Goossens, G
      Processor modeling and code selection for retargetable compilation

      ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
    20. Huang, IJ
      Co-synthesis of pipeline structures and instruction reordering constraintsfor instruction set processors

      ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
    21. Sivaswamy, J; Salcic, Z; Ling, KL
      A real-time implementation of nonlinear unsharp masking with FPLDs

      REAL-TIME IMAGING
    22. Dean, A; Garrett, D; Stan, MR; Ventrone, S
      Low power design for ASIC cores

      VLSI DESIGN
    23. Shin, Y; Choi, K; Sakurai, T
      Power-conscious scheduling for real-time embedded systems design

      VLSI DESIGN
    24. Kin, J; Lee, C; Mangione-Smith, WH; Potkonjak, M
      Exploring the diversity of multimedia systems

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    25. Gschwind, M; Salapura, V; Maurer, D
      FPGA prototyping of a RISC processor core for embedded applications

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    26. Lin, R
      Reconfigurable parallel inner product processor architectures

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    27. Parhi, KK
      Approaches to low-power implementations of DSP systems

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    28. Ma, J; Parhi, KK; Deprettere, EF
      A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms

      IEEE TRANSACTIONS ON SIGNAL PROCESSING
    29. Ahn, JW; Sung, W
      Multimedia processor-based implementation of an error-diffusion halftoningalgorithm exploiting subword parallelism

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    30. Hsiao, SF; Shiue, WR
      A new hardware-efficient algorithm and architecture for computation of 2-DDCTs on a linear array

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY
    31. Hsu, CH; Chung, YC; Yang, DL; Dow, CR
      A generalized processor mapping technique for array redistribution

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    32. Thanalapati, T; Dandamudi, S
      An efficient adaptive scheduling scheme for distributed memory multicomputers

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    33. Mu'alem, AW; Feitelson, DG
      Utilization, predictability, workloads, and user runtime estimates in scheduling the IBM SP2 with backfilling

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    34. Hou, Y; Wang, CM; Ku, CY; Hsu, LH
      Optimal processor mapping for linear-complement communication on hypercubes

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    35. Chen, HL; Hu, SH
      Submesh determination in faulty tori and meshes

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    36. Pan, Y; Zheng, SQ; Li, KQ; Shen, H
      An improved generalization of mesh-connected computers with multiple buses

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    37. Parhami, B; Kwai, DM
      A unified formulation of honeycomb and diamond networks

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    38. Svolos, AI; Konstantopoulos, CG; Kaklamanis, C
      Efficient primitive binary morphological algorithms on a massively parallel processor

      JOURNAL OF ELECTRONIC IMAGING
    39. Liang, R; Jusko, O; Ludicke, F; Neugebauer, M
      A novel piezo vibration platform for probe dynamic performance calibration

      MEASUREMENT SCIENCE & TECHNOLOGY
    40. Avci, AK; Onsan, ZI; Trimm, DL
      On-board fuel conversion for hydrogen fuel cells: comparison of different fuels by computer simulations

      APPLIED CATALYSIS A-GENERAL
    41. Moon, DJ; Sreekumar, K; Lee, SD; Lee, BG; Kim, HS
      Studies on gasoline fuel processor system for fuel-cell powered vehicles application

      APPLIED CATALYSIS A-GENERAL
    42. Elmaghraby, SE
      On the optimal release time of jobs with random processing times, with extensions to other criteria

      INTERNATIONAL JOURNAL OF PRODUCTION ECONOMICS
    43. Ortega, A; Marco, S; Perera, A; Sundic, T; Pardo, A; Samitier, J
      An intelligent detector based on temperature modulation of a gas sensor with a digital signal processor

      SENSORS AND ACTUATORS B-CHEMICAL
    44. Kranitis, N; Paschalis, A; Gizopoulos, D; Psarakis, M; Zorian, Y
      An effective deterministic BIST scheme for shifter/accumulator pairs in datapaths

      JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
    45. Vrbik, J
      Quaternionic processor

      CELESTIAL MECHANICS & DYNAMICAL ASTRONOMY
    46. Vrbik, J
      Quaternionic processor

      CELESTIAL MECHANICS & DYNAMICAL ASTRONOMY
    47. Guo, MY; Nakata, I
      A framework for efficient data redistribution on distributed memory multicomputers

      JOURNAL OF SUPERCOMPUTING
    48. Fimmel, D; Merker, R
      Design of processor arrays for reconfigurable architectures

      JOURNAL OF SUPERCOMPUTING
    49. Cha, HJ; Lee, D
      H-BSP: A hierarchical BSP computation model

      JOURNAL OF SUPERCOMPUTING
    50. Takanami, I
      A graph-theoretic approach to minimizing the number of dangerous processors in fault-tolerant mesh-connected processor arrays

      IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
    51. Kamiura, N; Kodera, T; Matsui, N
      Design of fault tolerant multistage interconnection networks with dilated links

      IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
    52. Murakami, K; Magoshi, H
      Trends in high-performance, low-power processor architectures

      IEICE TRANSACTIONS ON ELECTRONICS
    53. Uchiyama, K; Arakawa, F; Saito, Y; Noguchi, K; Hasegawa, A; Yoshioka, S; Irie, N; Kitahara, T; Debbage, M; Sturges, A
      Embedded processor core with 64-bit architecture and its system-on-chip integration for digital consumer products

      IEICE TRANSACTIONS ON ELECTRONICS
    54. Ohira, H; Kamemaru, T; Suzuki, H; Asano, K; Yoshimoto, M
      A low power media processor core performable CIF30 fr/s MPEG4/H26x video codec

      IEICE TRANSACTIONS ON ELECTRONICS
    55. Kim, JM; Shin, YS; Hwang, IG; Lee, KS; Han, SI; Park, SG; Chae, SI
      A high-performance videophone chip with dual multimedia VLIW processor cores

      IEICE TRANSACTIONS ON ELECTRONICS
    56. Segawa, H; Matsuura, Y; Kumaki, S; Matsumura, T; Scotzniovsky, S; Murayama, S; Wada, T; Harada, A; Ohara, E; Asano, K; Yoshida, T; Horiba, Y
      An embedded software scheme for a real-time single-chip MPEG-2 encoder system with a VLIW media processor core

      IEICE TRANSACTIONS ON ELECTRONICS
    57. Ozawa, M; Imai, M; Ueno, Y; Nakamura, H; Nanya, T
      A cascade ALU architecture for asynchronous super-scalar processors

      IEICE TRANSACTIONS ON ELECTRONICS
    58. Matsumura, T; Kumaki, S; Segawa, H; Ishihara, K; Hanami, A; Matsuura, Y; Scotzniovsky, S; Takata, H; Yamada, A; Murayama, S; Wada, T; Ohira, H; Shimada, T; Asano, K; Yoshida, T; Yoshimoto, M; Tsuchihashi, K; Horiba, Y
      A single-chip MPEG-2 422P@ML video, audio, and system encoder with a 162 MHz media-processor core and dual motion estimation cores

      IEICE TRANSACTIONS ON ELECTRONICS
    59. Mizutani, N; Muramatsu, S; Kikuchi, H
      Memory access estimation of filter bank implementation on different DSP architectures

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    60. Kim, SM; Lee, JW; Lee, SH; Choi, SB
      Analytical models and performance analyses of instruction fetch on superscalar processors

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    61. Ge, QW; Tanaka, A
      An effective dynamic priority list for 2-processor scheduling of program nets

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    62. Lee, DH; Park, IC; Kyung, CM
      Synthesis of application-specific coprocessor for core-based ASIC design

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    63. Togawa, N; Kataoka, Y; Miyaoka, Y; Yanagisawa, M; Ohtsuki, T
      Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    64. Moshnyaga, VG; Tsuji, H
      Reducing cache energy dissipation by using dual voltage supply

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    65. Togawa, N; Sakurai, T; Yanagisawa, M; Ohtsuki, T
      A new hardware/software partitioning algorithm for DSP processor cores with two types of register files

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    66. Suzuki, H; Kawai, H; Makino, H; Matsuda, Y
      Novel VLIW code compaction method for a 3D geometry processor

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    67. Yasuura, H
      Towards the system LSI design technology

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    68. Hong, CC; Lee, CY; Hsieh, YL; Liu, CC; Fong, IK; Hwu, JG
      Improvement in oxide thickness uniformity by repeated spike oxidation

      IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
    69. Detti, P; Pacciarelli, D
      A branch and bound algorithm for the minimum storage-time sequencing problem

      NAVAL RESEARCH LOGISTICS
    70. Exposito, AG; Jaen, AD
      Reduced substation models for generalized state estimation

      IEEE TRANSACTIONS ON POWER SYSTEMS
    71. Michaud, P; Seznec, A; Jourdan, S
      An exploration of instruction fetch requirement in out-of-order superscalar processors

      INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING
    72. Klauser, A; Manne, S; Grunwald, D
      Selective branch inversion: Confidence estimation for branch predictors

      INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING
    73. Zheng, SQ; Li, KQ; Pan, Y; Pinotti, MC
      Generalized coincident pulse technique and new addressing schemes for time-division multiplexing optical buses

      JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
    74. Mahapatra, NR; Dutt, S
      Hardware-efficient and highly reconfigurable 4-and 2-track fault-tolerant designs for mesh-connected arrays

      JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
    75. Ohgi, N
      Overview of NEC activity related to International Space Station

      NEC RESEARCH & DEVELOPMENT
    76. Azizoglu, M; Webster, S
      Scheduling a batch processing machine with incompatible job families

      COMPUTERS & INDUSTRIAL ENGINEERING
    77. Vieira, RC; Coutinho, ALGA; Alves, JLD; Biscaia, EC
      Dynamic simulation and optimization of multitubular reactors

      LATIN AMERICAN APPLIED RESEARCH
    78. Konishi, T; Furukawa, H; Ichioka, Y; Nakagawa, K; Melloch, MR; Nolte, DD
      Direct time-space conversion of ultra-fast pulses based on interferometrictime-of-flight cross correlation using a fast optical addressable spatial light modulator

      OPTICAL AND QUANTUM ELECTRONICS
    79. Makinen, J; Marttila, H; Viljanen, MK
      Automated purification of Borrelia burgdorferi s.l. PCR products with KingFisher (TM) magnetic particle processor prior to genome sequencing

      JOURNAL OF MAGNETISM AND MAGNETIC MATERIALS
    80. Helms, J; Muller, J; Schon, F; Winkler, F; Moser, L; Shehata-Dieler, W; Kastenbauer, E; Baumann, U; Rasp, G; Schorn, K; Esser, B; Baumgartner, W; Hamzavi, S; Gstottner, W; Westhofen, M; Doring, W; Dujardin, H; Albegger, K; Mair, A; Zenner, HP; Haferkamp, C; Schmitz-Salue, C; Arold, R; Sesterhenn, G; Jahnke, V; Wagner, H; Grabel, S; Bockmuhl, U; Hausler, R; Vischer, M; Kompis, M; Hildmann, H; Radu, HJ; Stark, T; Engel, A; Hildmann, A; Streitberger, C; Huttenbrink, KB; Muller-Aschoff, E; Hofmann, G; Seeling, K; Hloucal, U; von Ilberg, C; Kiefer, J; Pfennigdorff, T; Gall, V; Breitfuss, A; Stelzig, Y; Begall, K; Hey, M; Vorwerk, W; Thumfart, W; Gunkel, A; Zorowka, P; Stephan, K; Gammert, C; Mathis, A; DeMin, N; Freigang, B; Ziese, M; Stutzel, A; von Specht, H; Arnold, W; Brockmeier, SJ; Ebenhoch, H; Steinhoff, A; Zierhofer, C; Zwicknagl, M; Stobich, B
      Comparison of the TEMPO plus ear-level speech processor and the CISPRO plus body-worn processor in adult MED-EL cochlear implant users

      ORL-JOURNAL FOR OTO-RHINO-LARYNGOLOGY AND ITS RELATED SPECIALTIES
    81. Rhodes, DL; Wolf, W
      RAGS - Real-analysis ALAP-guided synthesis

      IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    82. Terzic, B; Jadric, M
      Design and implementation of the extended Kalman filter for the speed and rotor position estimation of brushless DC motor

      IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
    83. Chen, SL; Liu, YC
      Post-processor development for a six degrees-of-freedom parallel-link machine tool

      INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY
    84. Kumaran, K; Mandjes, M
      The buffer-bandwidth trade-off curve is convex

      QUEUEING SYSTEMS
    85. Huang, HY; Chen, YS; Hsu, WH
      Primary-view perception on a gray image: Region segmentation and association

      JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS
    86. Huang, JM
      A fault-tolerant connected-cycle-based mesh architecture

      JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS
    87. Wouters, J; Vanden Berghe, J
      Speech recognition in noise for cochlear implantees with a two-microphone monaural adaptive noise reduction system

      EAR AND HEARING
    88. Chlebus, BS; De Prisco, R; Shvartsman, AA
      Performing tasks on synchronous restartable message-passing processors

      DISTRIBUTED COMPUTING
    89. Okabe, T; Nakamura, K; Asano, T
      Image quality of dry-processed film

      COMPUTER METHODS AND PROGRAMS IN BIOMEDICINE
    90. Tanida, H; Ishii, M
      X-ray absorption spectroscopy of diluted system by undulator photon sourceand multi-element solid-state detector

      NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT
    91. Eremenko, YA; Kalinin, YG; Martyanov, IS; Sadykov, TK; Zastrozhnova, NN
      Multi-channel analog processor with 5 x 10(5): 1 dynamic range for registration of interaction at super-high energies in the cosmic rays

      NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT
    92. Goossens, B
      Handling 16 instructions per cycle in a superscalar processor

      FUTURE GENERATION COMPUTER SYSTEMS
    93. Jovanovic, Z; Maric, S
      A heuristic algorithm for dynamic task scheduling in highly parallel computing systems

      FUTURE GENERATION COMPUTER SYSTEMS
    94. Pean, DL; Wu, CC; Chua, HT; Chen, C
      Design of a scalable multiprocessor architecture and its simulation

      JOURNAL OF SYSTEMS AND SOFTWARE
    95. Leung, A; Palem, KV; Pnueli, A
      Scheduling time-constrained instructions on pipelined processors

      ACM TRANSACTIONS ON PROGRAMMING LANGUAGES AND SYSTEMS
    96. Yang, HY; Mertoguno, SJ; Bourbakis, NG
      Design of the Kydon-RISC processor

      MICROPROCESSORS AND MICROSYSTEMS
    97. Soon, IY; Yeo, CK; Ng, HC
      An analogue video interface for general-purpose DSP

      MICROPROCESSORS AND MICROSYSTEMS
    98. Niemier, MT; Kogge, PM
      Problems in designing with QCAs: Layout equals timing

      INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
    99. Tseng, PC; Chen, CK; Chen, LG
      CDSP: An application-specific digital signal processor for third generation wireless communications

      IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
    100. Hur, BS; Kang, MG
      High definition color interpolation scheme for progressive scan CCD image sensor

      IEEE TRANSACTIONS ON CONSUMER ELECTRONICS


ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 13/08/20 alle ore 02:53:48