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La ricerca find articoli where soggetti phrase all words 'PIPELINING' sort by level,fasc_key/DESCEND, pagina_ini_num/ASCEND ha restituito 128 riferimenti
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    1. Granston, E; Stotzer, E; Zbiciak, J
      Software pipelining irregular loops on the TMS320C6000 VLIW DSP architecture

      ACM SIGPLAN NOTICES
    2. Living, J; Moniri, M; Tennakoon, SB
      Efficient recursive digital filters using combined look-ahead denominator distribution and numerator decomposition

      JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
    3. Shenoy, N; Choudhary, A; Banerjee, P
      An algorithm for synthesis of large time-constrained heterogeneous adaptive systems

      ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
    4. Bakshi, S; Gajski, DD
      Performance-constrained hierarchical pipelining for behaviors, loops, and operations

      ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
    5. Sodagar, AM; Lahiji, GR
      A pipelined ROM-less architecture for sine-output direct digital frequencysynthesizers using the second-order parabolic approximation

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    6. Chi, ZP; Ma, J; Parhi, KK
      Hybrid annihilation transformation (HAT) for pipelining QRD-based least-square adaptive filters

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    7. Kazi, IH; Lija, DJ
      Coarse-grained thread pipelining: A speculative parallel execution model for shared-memory multiprocessors

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    8. Moritz, CA; Frank, MI
      LoGPC: Modeling network contention in message-passing programs

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    9. Tai, HM; Jing, CY
      Design and efficient implementation of a modulated complex lapped transform processor using pipelining technique

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    10. Weinhardt, M; Luk, W
      Pipeline vectorization

      IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
    11. Smith, SC; DeMara, RF; Yuan, JS; Hagedorn, M; Ferguson, D
      Delay-insensitive gate-level pipelining

      INTEGRATION-THE VLSI JOURNAL
    12. Schenk, O; Gartner, K; Fichtner, W; Stricker, A
      PARDISO: a high-performance serial and parallel sparse linear solver in semiconductor device simulation

      FUTURE GENERATION COMPUTER SYSTEMS
    13. Jing, WC; Zhou, G; Zhang, YM; Liu, W; Tian, JD; Zhang, X; Li, HF; Zhang, N
      Design and analysis of a scalable optical interconnection network for a computer cluster

      OPTICAL ENGINEERING
    14. Martin, AJ
      Towards an energy complexity of computation

      INFORMATION PROCESSING LETTERS
    15. Kozak, M; Kale, I
      A pipelined noise shaping coder for fractional-N frequency synthesis

      IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT
    16. Tyson, GS; Smelyanskiy, M; Davidson, ES
      Evaluating the use of register queues in software pipelined loops

      IEEE TRANSACTIONS ON COMPUTERS
    17. Llosa, J; Ayguade, E; Gonzalez, A; Valero, M; Eckhardt, J
      Lifetime-sensitive modulo scheduling in a production environment

      IEEE TRANSACTIONS ON COMPUTERS
    18. Haynal, S; Brewer, F
      Automata-based symbolic scheduling for looping DFGs

      IEEE TRANSACTIONS ON COMPUTERS
    19. Lopez, D; Llosa, J; Valero, M; Ayguade, E
      Cost-conscious strategies to increase performance of numerical programs onaggressive VLIW architectures

      IEEE TRANSACTIONS ON COMPUTERS
    20. Zalamea, J; Llosa, J; Ayguade, E; Valero, M
      Improved spill code generation for software pipelined loops

      ACM SIGPLAN NOTICES
    21. Milicev, D; Jovanovic, Z
      Sources of parallelism in software pipelining loops with conditional branches

      ACM SIGPLAN NOTICES
    22. Sanchez, JL; Garcia, JM
      Dynamic reconfiguration of node location in wormhole networks

      JOURNAL OF SYSTEMS ARCHITECTURE
    23. Nourani, M; Papachristou, C
      Stability-based algorithms for high-level synthesis of digital ASICs

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    24. Chung, JG; Kim, H; Parhi, KK
      Angle-constrained IIR filter pipelining for reduced coefficient sensitivities

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    25. Gao, LJ; Parhi, KK
      Hierarchical pipelining and folding of QRD-RLS adaptive filters and its application to digital beamforming

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    26. Bhattacharyya, SS; Sriram, S; Lee, EA
      Resynchronization for multiprocessor DSP systems

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS
    27. Ma, J; Parhi, KK; Hekstra, GJ; Deprettere, EF
      Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal mu-rotations

      IEEE TRANSACTIONS ON SIGNAL PROCESSING
    28. Silla, F; Duato, J
      On the use of virtual channels in networks of workstations with irregular topology

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    29. Lin, R; Nakano, K; Olariu, S; Pinotti, MC; Schwing, JL; Zomaya, AY
      Scalable hardware-algorithms for binary prefix sums

      IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    30. Darte, A; Huard, G
      Loop shifting for loop compaction

      INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING
    31. Lowenthal, DK
      Accurately selecting block size at runtime in pipelined parallel programs

      INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING
    32. Govindarajan, R; Rao, NSSN; Altman, ER; Guang, GR
      Enhanced co-scheduling: A software pipelining method using module-scheduled pipeline theory

      INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING
    33. Chatterjee, M; Banerjee, S; Pradhan, DK
      Buffer assignment algorithms on data driven ASICs

      IEEE TRANSACTIONS ON COMPUTERS
    34. Tongsima, S; Sha, EHM; Chantrapornchai, C; Surma, DR; Passos, NL
      Probabilistic loop scheduling for applications with uncertain execution time

      IEEE TRANSACTIONS ON COMPUTERS
    35. Wang, YT; Razavi, B
      An 8-bit 150-MHz CMOS A/D converter

      IEEE JOURNAL OF SOLID-STATE CIRCUITS
    36. Sanchez, F; Cortadella, J; Badia, RM
      Optimal exploration of the unrolling degree for software pipelining

      JOURNAL OF SYSTEMS ARCHITECTURE
    37. Ghose, K; Desai, KR; Kogge, PM
      Accelerating object-oriented applications using method lookup caches and register windowing

      JOURNAL OF SYSTEMS ARCHITECTURE
    38. Mertzios, BG; Grigoriadis, GK
      Fast implementation of forward robot kinematics of position with distributed arithmetic architecture

      IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART A-SYSTEMS AND HUMANS
    39. Bakshi, S; Gajski, DD
      Partitioning and pipelining for performance-constrained hardware/software systems

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    40. Li, CS; Sivarajan, KN; Messerschmitt, DG
      Statistical analysis of timing rules for high-speed synchronous VLSI systems

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    41. Yoo, JT; Gopalakrishnan, G; Smith, KF
      Timing constraints for high-speed counterflow-clocked pipelining

      IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
    42. Ascia, G; Catania, V; Russo, M
      VLSI hardware architecture for complex fuzzy systems

      IEEE TRANSACTIONS ON FUZZY SYSTEMS
    43. Kovalenko, NS; Metel'skii, VM
      Optimality of software resource structurization in distributed processing

      CYBERNETICS AND SYSTEMS ANALYSIS
    44. Shaw, AK; Ahmed, MI
      Pipelined recursive digital filters: A general look-ahead scheme and optimal approximation

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    45. Royo, D; Gonzalez, A; Valero-Garcia, M
      Low communication overhead Jacobi algorithms for eigenvalues computation on hypercubes

      JOURNAL OF SUPERCOMPUTING
    46. Fang, WH; Wu, ML
      Unified fully-pipelined VLSI implementations of the one- and two-dimensional real discrete trigonometric transforms

      IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
    47. Sanchez, J; Gonzalez, A
      Software data prefetching for software pipelined loops

      JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING
    48. Hoogerbrugge, J; Augusteijn, L; Trum, J; Van de Wiel, R
      A code compression system based on pipelined interpreters

      SOFTWARE-PRACTICE & EXPERIENCE
    49. Healy, CA; Arnold, RD; Mueller, F; Whalley, DB; Harmon, MG
      Bounding pipeline and instruction cache performance

      IEEE TRANSACTIONS ON COMPUTERS
    50. JOHNSON D; AKELLA V; STOTT B
      MICROPIPELINED ASYNCHRONOUS DISCRETE COSINE TRANSFORM (DCT IDCT) PROCESSOR/

      IEEE transactions on very large scale integration (VLSI) systems
    51. BURLESON WP; CIESIELSKI M; KLASS F; LIU WT
      WAVE-PIPELINING - A TUTORIAL AND RESEARCH SURVEY

      IEEE transactions on very large scale integration (VLSI) systems
    52. PAUL JM; MICKLE MH
      3-DIMENSIONAL COMPUTATIONAL PIPELINING WITH MINIMAL LATENCY AND MAXIMUM THROUGHPUT FOR L-U FACTORIZATION

      IEEE transactions on circuits and systems. 2, Analog and digital signal processing
    53. Chang, YN; Satyanarayana, JH; Parhi, KK
      Systematic design of high-speed and low-power digit-serial multipliers

      IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
    54. DELGADOFRIAS JG; NYATHI J; SUMMERVILLE DH
      A PROGRAMMABLE DYNAMIC INTERCONNECTION NETWORK ROUTER WITH HIDDEN REFRESH

      IEEE transactions on circuits and systems. 1, Fundamental theory andapplications
    55. IM GH; SHANBHAG NR
      A PIPELINED ADAPTIVE NEXT CANCELER

      IEEE transactions on signal processing
    56. CALLAND PY; DARTE A; ROBERT Y
      CIRCUIT RETIMING APPLIED TO DECOMPOSED SOFTWARE PIPELINING

      IEEE transactions on parallel and distributed systems
    57. HARADA A; NISHIKAWA K; KIYA H
      PIPELINED ARCHITECTURE OF THE LMS ADAPTIVE DIGITAL-FILTER WITH THE MINIMUM OUTPUT LATENCY

      IEICE transactions on fundamentals of electronics, communications and computer science
    58. ALTMAN ER; GAO GR
      OPTIMAL MODULO SCHEDULING THROUGH ENUMERATION

      International journal of parallel programming
    59. LLOSA J; AYGUADE E; VALERO M
      QUANTITATIVE-EVALUATION OF REGISTER PRESSURE ON SOFTWARE PIPELINED LOOPS

      International journal of parallel programming
    60. DONALDSON V; FERRANTE J
      ANALYZING ASYNCHRONOUS PIPELINE SCHEDULES

      International journal of parallel programming
    61. DECERIO LD; VALEROGARCIA M; GONZALEZ A
      A METHOD FOR EXPLOITING COMMUNICATION COMPUTATION OVERLAP IN HYPERCUBES/

      Parallel computing
    62. MERTZIOS BG
      FAST IMPLEMENTATION OF DIRECT ROBOT KINEMATICS WITH CORDIC SYSTOLIC ARRAYS

      International journal of computer mathematics
    63. BEKAKOS MP; EFREMIDES OB
      AN EFFICIENT APPROACH TO MAPPING LARGE ANNS ONTO FIXED SYSTOLIC ARCHITECTURES

      International journal of computer mathematics
    64. LLOSA J; VALERO M; AYGUADE E; GONZALEZ A
      MODULE SCHEDULING WITH REDUCED REGISTER PRESSURE

      I.E.E.E. transactions on computers
    65. TAKAHASHI M; HAMADA M; NISHIKAWA T; ARAKIDA H; FUJITA T; HATORI F; MITA S; SUZUKI K; CHIBA A; TERAZAWA T; SANO F; WATANABE Y; USAMI K; IGARASHI M; ISHIKAWA T; KANAZAWA M; KURODA T; FURUYAMA T
      A 60-MW MPEG4 VIDEO CODEC USING CLUSTERED VOLTAGE SCALING WITH VARIABLE SUPPLY-VOLTAGE SCHEME

      IEEE journal of solid-state circuits
    66. CHANG JM; PEDRAM M
      ENERGY MINIMIZATION USING MULTIPLE SUPPLY VOLTAGES

      IEEE transactions on very large scale integration (VLSI) systems
    67. NEKILI M; BOIS G; SAVARIA Y
      PIPELINED H-TREES FOR HIGH-SPEED CLOCKING OF LARGE INTEGRATED SYSTEMSIN PRESENCE OF PROCESS VARIATIONS

      IEEE transactions on very large scale integration (VLSI) systems
    68. SATYANARAYANA JH; PARHI KK
      A THEORETICAL APPROACH TO ESTIMATION OF BOUNDS ON POWER-CONSUMPTION IN DIGITAL MULTIPLIERS

      IEEE transactions on circuits and systems. 2, Analog and digital signal processing
    69. LI Y; PARHI KK
      STAR RECURSIVE LEAST-SQUARE LATTICE ADAPTIVE FILTERS

      IEEE transactions on circuits and systems. 2, Analog and digital signal processing
    70. HSIAO HI; CHEN MS; YU PS
      PARALLEL EXECUTION OF HASH JOINS IN PARALLEL DATABASES

      IEEE transactions on parallel and distributed systems
    71. YANG T; FU C
      HEURISTIC ALGORITHMS FOR SCHEDULING ITERATIVE TASK COMPUTATIONS ON DISTRIBUTED-MEMORY MACHINES

      IEEE transactions on parallel and distributed systems
    72. MERTZIOS BG; VENETSANOPOULOS AN
      FAST IMPLEMENTATION OF 3-D DIGITAL-FILTERS VIA SYSTOLIC ARRAY PROCESSORS

      Multidimensional systems and signal processing
    73. MATSUBARA K; NISHIKAWA K; KIYA H
      2-D PIPELINED ADAPTIVE FILTERS BASED ON 2-D DELAYED LMS-ALGORITHM

      IEICE transactions on fundamentals of electronics, communications and computer science
    74. ANDONOV R; RAJOPADHYE S
      OPTIMAL ORTHOGONAL TILING OF 2-D ITERATIONS

      Journal of parallel and distributed computing
    75. CHAO LF; LAPAUGH AS; SHA EHM
      ROTATION SCHEDULING - A LOOP PIPELINING ALGORITHM

      IEEE transactions on computer-aided design of integrated circuits and systems
    76. BRAUN M; EVEN G; WALLE T
      MIRRORING - A TECHNIQUE FOR PIPELINING SEMI-SYSTOLIC AND SYSTOLIC ARRAYS

      Integration
    77. MOON SM; EBCIOGLU K
      PARALLELIZING NONNUMERICAL CODE WITH SELECTIVE SCHEDULING AND SOFTWARE PIPELINING

      ACM transactions on programming languages and systems
    78. SHI HC; RITTER GX; WILSON JN
      A FAST GENERAL ALGORITHM FOR EXTRACTING IMAGE FEATURES ON SIMD MESH-CONNECTED COMPUTERS

      Pattern recognition
    79. KALISZ J; SZPLET R; PELKA R; PONIECKI A
      SINGLE-CHIP INTERPOLATING TIME COUNTER WITH 200-PS RESOLUTION AND 43-S RANGE

      IEEE transactions on instrumentation and measurement
    80. OLUKOTUN K; MUDGE TN; BROWN RB
      MULTILEVEL OPTIMIZATION OF PIPELINED CACHES

      I.E.E.E. transactions on computers
    81. MOYER GC; CLEMENTS M; LIU WT; SCHAFFER T; CAVIN RK
      THE DELAY VERNIER PATTERN GENERATION TECHNIQUE

      IEEE journal of solid-state circuits
    82. MICHAEL N; ARRATHOON R
      OPTOELECTRONIC PIPELINE ARCHITECTURE FOR MORPHOLOGICAL IMAGE-PROCESSING

      Applied optics
    83. BAKSHI S; GAJSKI DD
      COMPONENT SELECTION FOR HIGH-PERFORMANCE PIPELINES

      IEEE transactions on very large scale integration (VLSI) systems
    84. ALLEN JD; SCHIMMEL DE
      ISSUES IN THE DESIGN OF HIGH-PERFORMANCE SIMD ARCHITECTURES

      IEEE transactions on parallel and distributed systems
    85. PETERS JG; SYSKA M
      CIRCUIT-SWITCHED BROADCASTING IN TORUS NETWORKS

      IEEE transactions on parallel and distributed systems
    86. GOVINDARAJAN R; ALTMAN ER; GAO GR
      A FRAMEWORK FOR RESOURCE-CONSTRAINED RATE-OPTIMAL SOFTWARE PIPELINING

      IEEE transactions on parallel and distributed systems
    87. GRIGORIADIS GK; MERTZIOS BG
      IMPLEMENTATION OF THE VELOCITIES OF THE END-EFFECTOR WITH THE DISTRIBUTED ARITHMETIC ARCHITECTURE

      Journal of intelligent & robotic systems
    88. KOBAYASHI H; YAMANO K; KOKUBUN H; KOBAYASHI K
      A 50 MHZ CMOS PIPELINED MAJORITY LOGIC DECODER FOR (1057,813) DIFFERENCE-SET CYCLIC CODE

      IEICE transactions on fundamentals of electronics, communications and computer science
    89. STELLAKIS HM; MANOLAKOS ES
      ADAPTIVE COMPUTATION OF HIGHER-ORDER MOMENTS AND ITS SYSTOLIC REALIZATION

      International journal of adaptive control and signal processing
    90. EICHENBERGER AE; DAVIDSON ES; ABRAHAM SG
      MINIMIZING REGISTER REQUIREMENTS OF A MODULE SCHEDULE VIA OPTIMUM STAGE SCHEDULING

      International journal of parallel programming
    91. CALVIN C
      IMPLEMENTATION OF PARALLEL FFT ALGORITHMS ON DISTRIBUTED-MEMORY MACHINES WITH A MINIMUM OVERHEAD OF COMMUNICATION

      Parallel computing
    92. FORSELL MJ
      MINIMAL PIPELINE ARCHITECTURE - AN ALTERNATIVE TO SUPERSCALAR ARCHITECTURE

      Microprocessors and microsystems
    93. BARLOW JL; YOON PA
      MODIFYING THE SINGULAR-VALUE DECOMPOSITION ON THE CONNECTION MACHINE

      International journal of high speed computing
    94. PAUL JM; MICKLE MH
      3-DIMENSIONAL COMPUTATIONAL WAVE-FRONTS FOR MATRIX PRODUCT

      Computers & electrical engineering
    95. CHENG HD; XIA DC
      A NOVEL PARALLEL APPROACH TO CHARACTER-RECOGNITION AND ITS VLSI IMPLEMENTATION

      Pattern recognition
    96. POMERANZ I; REDDY SM
      ON THE NUMBER OF TESTS TO DETECT ALL PATH DELAY FAULTS IN COMBINATIONAL LOGIC-CIRCUITS

      I.E.E.E. transactions on computers
    97. GHOSH D; NANDY SK
      DESIGN AND REALIZATION OF HIGH-PERFORMANCE WAVE-PIPELINED 8 X 8 B MULTIPLIER IN CMOS TECHNOLOGY

      IEEE transactions on very large scale integration (VLSI) systems
    98. AIKEN A; NICOLAU A; NOVACK S
      RESOURCE-CONSTRAINED SOFTWARE PIPELINING

      IEEE transactions on parallel and distributed systems
    99. CHEN MS; LO ML; YU PS; YOUNG HC
      APPLYING SEGMENTED RIGHT-DEEP TREES TO PIPELINING MULTIPLE HASH JOINS

      IEEE transactions on knowledge and data engineering
    100. SANO M; SHIMOGORI S; HIROSE F
      MINCUT PARTITIONING ACCELERATION USING HARDWARE CAD ACCELERATOR TP5000

      IEICE transactions on fundamentals of electronics, communications and computer science


ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 15/08/20 alle ore 02:28:57