Catalogo Articoli (Spogli Riviste)

OPAC HELP

Titolo:
Memory characteristics of Au/PZT/BIT/p-Si ferroelectric diode
Autore:
Wang, H; Yu, J; Dong, XM; Zhou, WL; Wang, YB; Zheng, YK; Zhao, JH;
Indirizzi:
Huazhong Univ Sci & Technol, Dept Elect Sci & Technol, Wuhan 430074, Peoples R China Huazhong Univ Sci & Technol Wuhan Peoples R China 430074 Peoples R China Guilin Inst Elect Technol, Dept Elect & Informat, Guilin 541004, Peoples RChina Guilin Inst Elect Technol Guilin Peoples R China 541004 , Peoples RChina
Titolo Testata:
SCIENCE IN CHINA SERIES E-TECHNOLOGICAL SCIENCES
fascicolo: 3, volume: 44, anno: 2001,
pagine: 274 - 279
SICI:
2095-0624(200106)44:3<274:MCOAFD>2.0.ZU;2-X
Fonte:
ISI
Lingua:
ENG
Soggetto:
FATIGUE; FILMS;
Keywords:
ferroelectric films; memory diode; Pb(Zr0.52Ti0.43)O-3; Bi4Ti3O12;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
11
Recensione:
Indirizzi per estratti:
Indirizzo: Wang, H Huazhong Univ Sci & Technol, Dept Elect Sci & Technol, Wuhan 430074, Peoples R China Huazhong Univ Sci & Technol Wuhan Peoples R China 430074 R China
Citazione:
H. Wang et al., "Memory characteristics of Au/PZT/BIT/p-Si ferroelectric diode", SCI CHINA E, 44(3), 2001, pp. 274-279

Abstract

A ferroelectric memory diode consisting of Au/PZT/BIT/pSi multilayer configuration has been fabricated by pulsed laser deposition (PLD) technique. The ferroelectric properties and the memory characteristics are investigated. The P-E curve of the PZT/BIT/p-Si films system had an asymmetry saturated hysteresls loop with P-r = 15 muC/cm(2) acid E-0 = 48 kV/cm, and the decay in remanent polarization was only 10% after 10(9) switching cycles, meanwhile the increase in coercive field was 12%. The CV hysteresis loop and the I-V curve showed a memory effect derived from the ferroelectric polarizationof PZT/BIT films, and the current density was 6.7 x 10(-8) A/cm(2) at a voltage of + 4V. Our diode had nonvolatile and nondestructive memory readout operation. There was a read current disparity of 0.05 muA for logic "1" andlogic "0" at a reed voltage of + 2V, and the stored logical value ("1" or "0") could be read out In 30 min.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 21/01/20 alle ore 06:57:39