Catalogo Articoli (Spogli Riviste)

OPAC HELP

Titolo:
3-D ICs: A novel chip design for improving deep-submicrometer interconnectperformance and systems-on-chip integration
Autore:
Banerjee, K; Souri, SJ; Kapur, P; Saraswat, KC;
Indirizzi:
Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA Stanford Univ Stanford CA USA 94305 tegrated Syst, Stanford, CA 94305 USA
Titolo Testata:
PROCEEDINGS OF THE IEEE
fascicolo: 5, volume: 89, anno: 2001,
pagine: 602 - 633
SICI:
0018-9219(200105)89:5<602:3IANCD>2.0.ZU;2-5
Fonte:
ISI
Lingua:
ENG
Soggetto:
THIN-FILM TRANSISTORS; LOW-TEMPERATURE; MQW MODULATORS; VLSI CIRCUITS; LOW-POWER; SILICON; CMOS; TECHNOLOGY; TFTS; CRYSTALLIZATION;
Keywords:
3-D ICs; heterogeneous integration; interconnect performance; optical I/Os; power dissipation; system interconnects; system-on-a-chip; design; VLSI design;
Tipo documento:
Review
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
129
Recensione:
Indirizzi per estratti:
Indirizzo: Banerjee, K Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA Stanford Univ Stanford CA USA 94305 t, Stanford, CA 94305 USA
Citazione:
K. Banerjee et al., "3-D ICs: A novel chip design for improving deep-submicrometer interconnectperformance and systems-on-chip integration", P IEEE, 89(5), 2001, pp. 602-633

Abstract

Performance of deep-submicrometer ver large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paperanalyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnectrelated problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply divining a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can he achieved. without the aid of any other circuit ordesign innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferringthe repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in hear sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design is sues have alsobeen discussed with especial attention to SoC design strategies. Finally, some of the promising technologies for manufacturing 3-D ICs have been outlined.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 04/12/20 alle ore 09:47:01