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Titolo:
Instruction fetch architectures and code layout optimizations
Autore:
Ramirez, A; Larriba-Pey, JL; Valero, M;
Indirizzi:
Univ Politecn Catalunya, ES-08034 Barcelona, Spain Univ Politecn Catalunya Barcelona Spain ES-08034 -08034 Barcelona, Spain
Titolo Testata:
PROCEEDINGS OF THE IEEE
fascicolo: 11, volume: 89, anno: 2001,
pagine: 1588 - 1609
SICI:
0018-9219(200111)89:11<1588:IFAACL>2.0.ZU;2-T
Fonte:
ISI
Lingua:
ENG
Soggetto:
PREDICTORS;
Keywords:
branch prediction; code layout; instruction fetch; trace cache;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
65
Recensione:
Indirizzi per estratti:
Indirizzo: Ramirez, A Univ Politecn Catalunya, D6, ES-08034 Barcelona, Spain Univ Politecn Catalunya D6 Barcelona Spain ES-08034 ona, Spain
Citazione:
A. Ramirez et al., "Instruction fetch architectures and code layout optimizations", P IEEE, 89(11), 2001, pp. 1588-1609

Abstract

The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing a higher performance processor implies balancing all the pipeline stages to ensure that overall perfomance is not dominated by any of them. This means that a faster execution engine also requires a faster fetch engine, to ensure that it is possible to read and decode enough instructions to keep the pipeline fill and the functional units bush. This paper explores the challenges faced by the instruction fetch stage for a variety of processor designs, from early pipelined processors, to the more aggressive wide issue superscalars. We describe the different fetch engines proposed in the literature, the performance issues involved, and some of the proposed improvements. We also show how compiler techniques that optimize the layout of the code in memory can be used to improve the fetch performance of the different engines described. Overall, we show how instruction fetch has evolved from fetching one instruction every, few cycles, to fetching one instruction per cycle, to fetching a full basic block per cycle, to several basic blocks per cycle: the evolution of the mechanism surrounding the instruction cache, and the differentcompiler optimizations used to better employ these mechanisms.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 14/07/20 alle ore 09:32:46