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Titolo:
Asynchronous current-mode multiple-valued VLSI system based on two-color two-rail coding
Autore:
Hanyu, T; Kameyama, M;
Indirizzi:
Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 9808579, Japan Tohoku Univ Sendai Miyagi Japan 9808579 ci, Sendai, Miyagi 9808579, Japan
Titolo Testata:
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS
fascicolo: 11, volume: 84, anno: 2001,
pagine: 60 - 67
SICI:
8756-663X(2001)84:11<60:ACMVSB>2.0.ZU;2-1
Fonte:
ISI
Lingua:
ENG
Soggetto:
TERNARY LOGIC; CIRCUITS;
Keywords:
multiple-valued two-color two-rail coding; handshake protocol; two-rail complementary signal; two-line differential logic; current-mode multiple-valued VLSI;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
14
Recensione:
Indirizzi per estratti:
Indirizzo: Hanyu, T Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 9808579, JapanTohoku Univ Sendai Miyagi Japan 9808579 i, Miyagi 9808579, Japan
Citazione:
T. Hanyu e M. Kameyama, "Asynchronous current-mode multiple-valued VLSI system based on two-color two-rail coding", ELEC C JP 2, 84(11), 2001, pp. 60-67

Abstract

In deep submicron VLSI, the asynchronous data protocol is a known technique to solve the performance degradation and increase in power dissipation problems arising from wiring such as cross queues. In this paper, we propose a new asynchronous multiple-valued data communication scheme without rest phases in multiple-valued data transfers. This scheme uses two-rail R-value complementary signal pairs, and the sum of the two-rail signal pair is always a constant for "valid data. " Along with defining a two-rail signal pair with each signal having an odd phase or an even phase, each signal level inthe even phase is set to always be larger than in the odd phase. The sum of a two-rail signal pair becomes the minimum and the maximum, respectively,of the odd phase and the even phase. Consequently, if the sum of the two-rail signal pair is examined, the monotonicity can be maintained in data transitions in two phases, and valid data can be detected by a simple threshold calculation. Furthermore, an asynchronous control circuit layout based onthe linear sum of a two-rail signal pair focuses on "the ability to implement the linear addition of current only at the connections" and clearly shows the ability to implement a more compact system than current-mode multiple-valued circuit systems. (C) 2001 Scripta Technica, Electron Comm Jpn Pt 2.

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Documento generato il 20/09/20 alle ore 00:01:17