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Titolo:
VLSI implementation of a 100-mu W multirate FSK receiver
Autore:
Grayver, E; Daneshrad, B;
Indirizzi:
Univ Calif Los Angeles, Dept Elect Engn, Wireless Integrated Syst Lab, LosAngeles, CA 90095 USA Univ Calif Los Angeles Los Angeles CA USA 90095 LosAngeles, CA 90095 USA
Titolo Testata:
IEEE JOURNAL OF SOLID-STATE CIRCUITS
fascicolo: 11, volume: 36, anno: 2001,
pagine: 1821 - 1828
SICI:
0018-9200(200111)36:11<1821:VIOA1W>2.0.ZU;2-N
Fonte:
ISI
Lingua:
ENG
Soggetto:
LOW-POWER;
Keywords:
discrete Fourier transforms; frequency modulation; satellite communication; signal sampling;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
24
Recensione:
Indirizzi per estratti:
Indirizzo: Grayver, E Univ Calif Los Angeles, Dept Elect Engn, Wireless Integrated Syst Lab, LosAngeles, CA 90095 USA Univ Calif Los Angeles Los Angeles CA USA90095 , CA 90095 USA
Citazione:
E. Grayver e B. Daneshrad, "VLSI implementation of a 100-mu W multirate FSK receiver", IEEE J SOLI, 36(11), 2001, pp. 1821-1828

Abstract

A very low-power frequency-shift keying (FSK) receiver has been designed for dual-purpose operation: deep space applications and general purpose baseband processing. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-b data processing together with an FFT-based detection scheme to enable power consumption dramatically, lower than a conventional implementation. A system/hardware co-design approach allows the use of a number of circuit-level power reduction techniques while still meeting system-level constraints. In particular, we designed a combination of fully parallel and word-serial decimation stages to simultaneously optimize power consumption and silicon area. We also designed a very efficient FFT block that uses approximate arithmetic and pruning to greatly reduce overall complexity. Additional modules, such as direct digital frequency synthesizer (DDFS) and magnitude computation, have also been optimized in view of the targeted system parameters: signal-to-noise ratio and bit-error rate. The entire architecture has been made maximally flexible and power efficient by utilizing local clock gating and simple interstage handshaking mechanism. The receiver has been implemented in 0.25-mum CMOS technology and takes up under 1 mm(2). The power consumption is below 100 muW for data rates below 20 kb/s. Rates up to 2 Mb/s are supported.

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Documento generato il 08/04/20 alle ore 12:07:37