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Titolo:
A 150-MHz graphics rendering processor with 256-Mb embedded DRAM
Autore:
Khan, AK; Magoshi, H; Matsumoto, T; Fujita, JI; Furuhashi, M; Imai, M; Kurose, Y; Sato, M; Sato, K; Yamashita, Y; Kwan, K; Le, DN; Yu, JH; Nguyen, T; Yang, S; Tsou, A; Chow, K; Shen, J; Li, M; Li, J; Zhao, H; Yoshida, K;
Indirizzi:
Simplex Solut Inc, Sunnyvale, CA 94086 USA Simplex Solut Inc Sunnyvale CAUSA 94086 lut Inc, Sunnyvale, CA 94086 USA Sony Comp Entertainment Inc, Tokyo, Japan Sony Comp Entertainment Inc Tokyo Japan Entertainment Inc, Tokyo, Japan Sony Corp, S&S Architecture Ctr, Tokyo, Japan Sony Corp Tokyo JapanSony Corp, S&S Architecture Ctr, Tokyo, Japan Sony Kihara Res Ctr Inc, Tokyo, Japan Sony Kihara Res Ctr Inc Tokyo Japan ny Kihara Res Ctr Inc, Tokyo, Japan Sony LSI Design Inc, Kanagawa, Japan Sony LSI Design Inc Kanagawa JapanSony LSI Design Inc, Kanagawa, Japan
Titolo Testata:
IEEE JOURNAL OF SOLID-STATE CIRCUITS
fascicolo: 11, volume: 36, anno: 2001,
pagine: 1775 - 1784
SICI:
0018-9200(200111)36:11<1775:A1GRPW>2.0.ZU;2-A
Fonte:
ISI
Lingua:
ENG
Keywords:
delay estimation; design methodology; signal integrity; very large-scale integration design;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
7
Recensione:
Indirizzi per estratti:
Indirizzo: Khan, AK Simplex Solut Inc, Sunnyvale, CA 94086 USA Simplex Solut Inc Sunnyvale CA USA 94086 Sunnyvale, CA 94086 USA
Citazione:
A.K. Khan et al., "A 150-MHz graphics rendering processor with 256-Mb embedded DRAM", IEEE J SOLI, 36(11), 2001, pp. 1775-1784

Abstract

A 150-MHz graphics rendering processor with an integrated 256-Mb embedded DRAM, delivering a rendering rate of 75 M polygons/s, is presented. 287.5 Mtransistors are integrated on a 21.3 x 21.7 mm(2) die in a 0.18-mum embedded DRAM CMOS process with six layers of metal. Design methodologies for hierarchical electrical and physical design of this very large-scale IC, including power distribution, fully hierarchical timing design, and verificationutilizing a newly developed nonlinear model, clock design, propagation delay, and crosstalk noise management in multimillimeter RC transmission lines, are presented.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 05/12/20 alle ore 19:46:43