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Titolo:
A new poly-Si TFT structure with air cavities at the gate-oxide edges
Autore:
Lee, MC; Jung, SH; Song, IH; Han, MK;
Indirizzi:
Seoul Natl Univ, Sch Elect Engn, Seoul, South Korea Seoul Natl Univ Seoul South Korea v, Sch Elect Engn, Seoul, South Korea
Titolo Testata:
IEEE ELECTRON DEVICE LETTERS
fascicolo: 11, volume: 22, anno: 2001,
pagine: 539 - 541
SICI:
0741-3106(200111)22:11<539:ANPTSW>2.0.ZU;2-U
Fonte:
ISI
Lingua:
ENG
Soggetto:
THIN-FILM TRANSISTORS; GAP;
Keywords:
air cavity; poly-Si TFT; stability; threshold voltage shift; vertical electric field;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
12
Recensione:
Indirizzi per estratti:
Indirizzo: Lee, MC Seoul Natl Univ, Sch Elect Engn, Seoul, South Korea Seoul Natl Univ Seoul South Korea lect Engn, Seoul, South Korea
Citazione:
M.C. Lee et al., "A new poly-Si TFT structure with air cavities at the gate-oxide edges", IEEE ELEC D, 22(11), 2001, pp. 539-541

Abstract

We propose a new poly-Si TFT structure employing air cavities at the edgesof gate oxide in order to reduce the threshold voltage shift after electrical stress and to decrease a large leakage current. Due to the low dielectric constant of air, the air cavity behaves as a thick insulator reducing the vertical electric field near the drain, so that poly-Si region under air cavity acts as an offset. The new poly-Si TFT structure has been successfully fabricated by employing wet etching of the gate oxide followed by atmospheric pressure chemical vapor deposition (APCVD) oxide deposition. Our experimental results show that the leakage current is considerably reduced without the decrease of the on-current and the device stability such as threshold voltage shift under the high-gate bias is also improved.

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Documento generato il 30/11/20 alle ore 12:14:14