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Titolo:
Morphable cache architectures: Potential benefits
Autore:
Kadayif, I; Kandemir, M; Vijaykrishnan, N; Irwin, MJ; Ramanujam, J;
Indirizzi:
Penn State Univ, Microsyst Design Lab, University Pk, PA 16802 USA Penn State Univ University Pk PA USA 16802 b, University Pk, PA 16802 USA
Titolo Testata:
ACM SIGPLAN NOTICES
fascicolo: 8, volume: 36, anno: 2001,
pagine: 128 - 137
SICI:
1523-2867(200108)36:8<128:MCAPB>2.0.ZU;2-S
Fonte:
ISI
Lingua:
ENG
Soggetto:
MEMORY;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
28
Recensione:
Indirizzi per estratti:
Indirizzo: Kadayif, I Penn State Univ, Microsyst Design Lab, University Pk, PA 16802 USA Penn State Univ University Pk PA USA 16802 ty Pk, PA 16802 USA
Citazione:
I. Kadayif et al., "Morphable cache architectures: Potential benefits", ACM SIGPL N, 36(8), 2001, pp. 128-137

Abstract

Computer architects have tried to mitigate the consequences of high memorylatencies using a variety techniques. An example of these techniques is multi-level caches to counteract the latency that results from having a memory that is slower than the processor. Recent research has demonstrated that compiler optimizations that modify data layouts and restructure computationcan be successful in improving memory system performance. However, in manycases, working with a fixed cache configuration prevents the application/compiler from obtaining the maximum performance. In addition, prompted by demand in portability, long battery life, and law-cost packaging, the computer industry has started viewing energy and power as decisive design factors,along with performance and cost. This makes the job of the compiler/user even more difficult as one needs to strike a balance between law power/energy consumption and high performance. Consequently, adapting the code to the underlying cache/memory hierarchy is becoming more and more difficult. In this paper, we take an alternate approach and attempt to adapt the cache architecture to the software needs. We focus on array-dominated applications and measure the potential benefits that could be gained from a morphable (reconfigurable) cache architecture. Our results show that not only different applications work best with different cache configurations, but also that different loop nests in a given application demand different configurations. Our results also indicate that the most suitable cache configuration for a given application or a single nest depends strongly on the objective function being optimized. For example, minimizing cache memory energy requires a different cache configuration for each nest than an objective which tries to minimize the overall memory system energy. Based on our experiments, we conclude that fine-grain (loop nest-level) cache configuration management is an important step for a solution to the challenging architecture/software tradeoffs awaiting system designers in the future.

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Documento generato il 26/01/20 alle ore 22:09:41