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Titolo:
Development of a CMOS imager LSI with focal-plane motion detectors
Autore:
Okamoto, F; Fujimoto, Y; Furumiya, M; Hatano, K; Nakashiba, Y; Yotsuyanagi, M;
Indirizzi:
NEC Corp Ltd, NEC Electron Devices, ULSI Device Dev Div, Sagamihara, Kanagawa 2291198, Japan NEC Corp Ltd Sagamihara Kanagawa Japan 2291198 a, Kanagawa 2291198, Japan NEC Corp Ltd, NEC Electron Devices, Syst LSI Design Engn Div, Kawasaki, Kanagawa 2110011, Japan NEC Corp Ltd Kawasaki Kanagawa Japan 2110011 aki, Kanagawa 2110011, Japan
Titolo Testata:
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS
fascicolo: 9, volume: 84, anno: 2001,
pagine: 28 - 35
SICI:
8756-663X(2001)84:9<28:DOACIL>2.0.ZU;2-C
Fonte:
ISI
Lingua:
ENG
Keywords:
CMOS imager; vision chip; motion detection; active pixels;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
7
Recensione:
Indirizzi per estratti:
Indirizzo: Okamoto, F NEC Corp Ltd, NEC Electron Devices, ULSI Device Dev Div, Sagamihara, Kanagawa 2291198, Japan NEC Corp Ltd Sagamihara Kanagawa Japan 2291198 2291198, Japan
Citazione:
F. Okamoto et al., "Development of a CMOS imager LSI with focal-plane motion detectors", ELEC C JP 2, 84(9), 2001, pp. 28-35

Abstract

A new CMOS imager having a motion detection function has been developed. This: CMOS imager can detect the motion of the image projected on a sensor array,. scan automatically only a partial area including a place where the motion is detected as the focus. As a result, reducing the amount of data transfer and improving the frame rate have become possible. The detection of a moving body can be performed by motion detector circuits, which operate regardless of the frame rate. The motion detectors are sparsely placed in the sensor array to maintain the high pixel density. Other circuit techniquesinclude the unity-gain pixel amps, and a multistage readout circuit. A 5.8- x 8.7-mm chip including 192 x 192 pixels and 7 x 7 motion detectors has been developed using a 0.35-mum CMOS three-layer metal process. technology. Experimental results have successfully confirmed the functions of the chip. (C) 2001 Scripta Technica.

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Documento generato il 27/01/20 alle ore 07:21:47