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Titolo:
Test generation for sequential circuits using state transition diagram andtest generation for combinatorial circuit part
Autore:
Hasegawa, T; Miura, K; Ohmameuda, T; Ito, H;
Indirizzi:
Chiba Univ, Fac Engn, Chiba 2638522, Japan Chiba Univ Chiba Japan 2638522 hiba Univ, Fac Engn, Chiba 2638522, Japan
Titolo Testata:
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS
fascicolo: 8, volume: 84, anno: 2001,
pagine: 20 - 28
SICI:
8756-663X(2001)84:8<20:TGFSCU>2.0.ZU;2-V
Fonte:
ISI
Lingua:
ENG
Soggetto:
VERIFICATION; MACHINES;
Keywords:
sequential circuit; test generation; state transition diagram; UIO sequence; activation vector set;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
19
Recensione:
Indirizzi per estratti:
Indirizzo: Hasegawa, T Chiba Univ, Fac Engn, Chiba 2638522, Japan Chiba Univ Chiba Japan 2638522 ac Engn, Chiba 2638522, Japan
Citazione:
T. Hasegawa et al., "Test generation for sequential circuits using state transition diagram andtest generation for combinatorial circuit part", ELEC C JP 2, 84(8), 2001, pp. 20-28

Abstract

This study deals with single stuck-at faults in sequential circuits; in particular, a test generation method featuring low generation complexity and short test sequences. With the proposed method, short test sequences are generated using shortest local connections between activation vector set found for combinatorial circuit part at gate level, and state transitions foundfrom state transition diagram at functional level. Generated test sequences are input sequences composed of subsequences referred to as single test sequences. Single test sequences are composed of state control sequences that control activation vectors and their states, and UIO (Unique Input/Output) sequences that con firm states after applying activation vectors. Test sequences are generated so as to locally minimize total length, of state control sequences and UIO sequences in connected single test sequences, which results in shorter test sequences as compared to previous generation methods. Evaluation experiments using MCNC benchmarks proved that test sequences generated by the proposed method were shorter by up to 28.8% as compared to previous methods while fault coverage was above 98% on the average. (C) 2001 Scripta Technica, Electron Comm Jpn.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 30/09/20 alle ore 09:44:02