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Titolo:
A hardware cost minimized fast Phong shader
Autore:
Shin, HC; Lee, JA; Kim, LS;
Indirizzi:
Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Tokai, Ibaraki, Japan Korea Adv Inst Sci & Technol Tokai Ibaraki Japan , Tokai, Ibaraki, Japan
Titolo Testata:
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
fascicolo: 2, volume: 9, anno: 2001,
pagine: 297 - 304
SICI:
1063-8210(200104)9:2<297:AHCMFP>2.0.ZU;2-0
Fonte:
ISI
Lingua:
ENG
Keywords:
adaptive computing; computer arithmetic; high performance; table complexity; tradeoffs;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
12
Recensione:
Indirizzi per estratti:
Indirizzo: Shin, HC Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Tokai, Ibaraki, Japan Korea Adv Inst Sci & Technol Tokai Ibaraki Japan Ibaraki, Japan
Citazione:
H.C. Shin et al., "A hardware cost minimized fast Phong shader", IEEE VLSI, 9(2), 2001, pp. 297-304

Abstract

One of the most successful algorithms that bring realism to the world of three-dimensional (3-D) image generation is the Phong shading, With the continuous improvement in VLSI technology and the demand for higher realism, this algorithm is a menable to the commercially available hardware implementation for real-time rendering in 3-D graphics. Taylor series approximation is appropriate for the hardware implementation of fast Phong shading. However, in this method, the exponentiation of the cosine term requires a very large ROM table, This paper describes the minimization of this overhead in terms of hardware size by proposing an adaptive-compressed nonuniform quantization method. With this method, the ROM table is reduced to 1/64th of the size required for a uniform quantization method while the picture quality ismaintained. Due to the reduced ROM table size, the size of the total hardware required for fast Phong shading is minimized to 1/56th of the original size.

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Documento generato il 28/01/20 alle ore 14:46:36