Catalogo Articoli (Spogli Riviste)

OPAC HELP

Titolo:
System-level performance analysis for designing on-chip communication architectures
Autore:
Lahiri, K; Raghunathan, A; Dey, S;
Indirizzi:
Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA Univ Calif San Diego La Jolla CA USA 92093 p Engn, La Jolla, CA 92093 USA NEC USA, Comp & Commun Res Labs, Princeton, NJ 08540 USA NEC USA Princeton NJ USA 08540 & Commun Res Labs, Princeton, NJ 08540 USA
Titolo Testata:
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
fascicolo: 6, volume: 20, anno: 2001,
pagine: 768 - 783
SICI:
0278-0070(200106)20:6<768:SPAFDO>2.0.ZU;2-T
Fonte:
ISI
Lingua:
ENG
Keywords:
bus architectures; communication architectures; on-chip communication; performance analysis; simulation trace; system-on-chip;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
17
Recensione:
Indirizzi per estratti:
Indirizzo: Lahiri, K Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093USA Univ Calif San Diego La Jolla CA USA 92093 Jolla, CA 92093 USA
Citazione:
K. Lahiri et al., "System-level performance analysis for designing on-chip communication architectures", IEEE COMP A, 20(6), 2001, pp. 768-783

Abstract

This paper presents a novel system-level performance analysis technique tosupport the design of custom communication architectures for system-on-chip integrated circuits. Our technique fills a gap in existing techniques forsystem-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e,g,, simulation of the complete system) or are not accurate enough to drive the design of the communication architecture (e,g,, techniques that perform a "static" analysis of the system performance). Our technique is based on a hybrid trace-based performance-analysis methodology in which an initial cosimulation of thesystem is performed with the communication described in an abstract manner(e,g,, as events or abstract data transfers). An abstract set of traces are extracted from the initial cosimulation containing necessary and sufficient information about the computations and communications of the system components, The system designer then specifies a communication architecture by:1) selecting a topology consisting of dedicated as well as shared communication channels (shared buses) interconnected by bridges; 2) mapping the abstract communications to paths in the communication architecture; and 3) customizing the protocol used for each channel. The traces extracted in the initial step are represented as a communication analysis graph (CAG) and an analysis of the CAG provides an estimate of the system performance as well as various statistics about the components and their communication, Experimental results indicate that our performance-analysis technique achieves accuracy comparable to complete system simulation tan average error of 1.88%) while being over two orders of magnitude faster.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 31/03/20 alle ore 08:54:28