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Titolo:
A fast algorithm for transistor folding
Autore:
Cheng, EYC; Sahni, S;
Indirizzi:
Univ Florida, Dept Comp & Informat Sci & Engn, Gainesville, FL 32611 USA Univ Florida Gainesville FL USA 32611 i & Engn, Gainesville, FL 32611 USA
Titolo Testata:
VLSI DESIGN
fascicolo: 1, volume: 12, anno: 2001,
pagine: 53 - 60
SICI:
1065-514X(2001)12:1<53:AFAFTF>2.0.ZU;2-3
Fonte:
ISI
Lingua:
ENG
Keywords:
transistor folding; row-based design; area minimization; complexity;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
10
Recensione:
Indirizzi per estratti:
Indirizzo: Cheng, EYC Univ Florida, Dept Comp & Informat Sci & Engn, Gainesville, FL 32611 USA Univ Florida Gainesville FL USA 32611 ainesville, FL 32611 USA
Citazione:
E.Y.C. Cheng e S. Sahni, "A fast algorithm for transistor folding", VLSI DESIGN, 12(1), 2001, pp. 53-60

Abstract

Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m(2) log m) algorithm to optimally fold m transistor pairs. In this paper we develop anO(m(2)) algorithm for optimal transistor folding. Our experiments indicatethat our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000).

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Documento generato il 23/01/20 alle ore 06:55:01