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Titolo:
Interconnect limits on gigascale integration (GSI) in the 21st century
Autore:
Davis, JA; Venkatesan, R; Kaloyeros, A; Beylansky, M; Souri, SJ; Banerjee, K; Saraswat, KC; Rahman, A; Reif, R; Meindl, JD;
Indirizzi:
Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA Georgia Inst Technol Atlanta GA USA 30332 omp Engn, Atlanta, GA 30332 USA SUNY Albany, Ctr Adv Thin Film Technol, Albany, NY 12222 USA SUNY Albany Albany NY USA 12222 v Thin Film Technol, Albany, NY 12222 USA SUNY Albany, Dept Phys, Albany, NY 12222 USA SUNY Albany Albany NY USA 12222 Y Albany, Dept Phys, Albany, NY 12222 USA Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA Stanford Univ Stanford CA USA 94305 pt Elect Engn, Stanford, CA 94305 USA MIT, Dept Elect Engn & Comp Sci, Cambridge, MA 02139 USA MIT Cambridge MAUSA 02139 Elect Engn & Comp Sci, Cambridge, MA 02139 USA
Titolo Testata:
PROCEEDINGS OF THE IEEE
fascicolo: 3, volume: 89, anno: 2001,
pagine: 305 - 324
SICI:
0018-9219(200103)89:3<305:ILOGI(>2.0.ZU;2-W
Fonte:
ISI
Lingua:
ENG
Soggetto:
FILMS; DELAY; TFTS;
Keywords:
crosstalk; epitaxial growth; interconnections; modeling; scattering; technology forecasting; thin films; thin film transistors; transmission lines; wafer bonding; wiring;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
51
Recensione:
Indirizzi per estratti:
Indirizzo: Davis, JA Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA Georgia Inst Technol Atlanta GA USA 30332 Atlanta, GA 30332 USA
Citazione:
J.A. Davis et al., "Interconnect limits on gigascale integration (GSI) in the 21st century", P IEEE, 89(3), 2001, pp. 305-324

Abstract

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication. and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction, At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. Ar the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. Ar the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in she every two years such that by2014 the number is significantly larger than ITRS projections. This resultemphasizes that changes in design, technology and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-Dintegration of transistors, which is expected to significantly improve interconnect performance. increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

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Documento generato il 30/11/20 alle ore 12:42:38