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Titolo:
A new intelligent SOFM-based sampling plan for advanced process control
Autore:
Lee, JH; You, SJ; Park, SC;
Indirizzi:
Korea Adv Inst Sci & Technol, Dept Ind Engn, Taejon 305701, South Korea Korea Adv Inst Sci & Technol Taejon South Korea 305701 5701, South Korea
Titolo Testata:
EXPERT SYSTEMS WITH APPLICATIONS
fascicolo: 2, volume: 20, anno: 2001,
pagine: 133 - 151
SICI:
0957-4174(200102)20:2<133:ANISSP>2.0.ZU;2-S
Fonte:
ISI
Lingua:
ENG
Soggetto:
FABRICATION; MODELS; SYSTEM;
Keywords:
Self-Oganizing Feature Map; neural network; sampling plan; process parameter; wafer bin map; semiconductor manufacturing;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
14
Recensione:
Indirizzi per estratti:
Indirizzo: Park, SC Korea Adv Inst Sci & Technol, Dept Ind Engn, 373-1 Kusong Dong, Taejon 305701, South Korea Korea Adv Inst Sci & Technol 373-1 Kusong Dong Taejon South Korea 305701
Citazione:
J.H. Lee et al., "A new intelligent SOFM-based sampling plan for advanced process control", EXPER SY AP, 20(2), 2001, pp. 133-151

Abstract

Sample measurement inspecting for a process parameter is a necessity in semiconductor manufacturing because of the prohibitive amount of time involved in 100% inspection while maintaining sensitivity to all types of defects and abnormality. In current industrial practice, sample measurement locations are chosen approximately evenly across the wafer, in order to have all regions of the wafer equally well represented, but they are not adequate if process-related defective chips are distributed with spatial pattern withinthe wafer. In this paper, we propose the methodology for generating effective measurement sampling plan for process parameter by applying the Self-Organizing Feature Map (SOFM) network, unsupervised learning neural network, to wafer bin map data within a certain time period. The sampling plan specifies which chips within the wafer need to be inspected, and how many chips within the wafer need to be inspected for a good sensitivity of 100% wafer coverage and defect detection. We finally illustrate the effectiveness of our proposedsampling plan using actual semiconductor fab data. (C) 2001 Elsevier Science Ltd. All rights reserved.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 26/09/20 alle ore 09:53:43