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Titolo:
Fully digital preambleless 40 Mbps QPSK receiver for burst transmission
Autore:
Kim, SG; Hwang, W; Kim, Y; Lee, Y; Choi, S; Kim, K;
Indirizzi:
Kwanju Inst Sci & Technol, Dept Informat & Commun, Kwangju 500712, South Korea Kwanju Inst Sci & Technol Kwangju South Korea 500712 500712, South Korea
Titolo Testata:
IEICE TRANSACTIONS ON ELECTRONICS
fascicolo: 2, volume: E84C, anno: 2001,
pagine: 175 - 182
SICI:
0916-8524(200102)E84C:2<175:FDP4MQ>2.0.ZU;2-8
Fonte:
ISI
Lingua:
ENG
Soggetto:
CARRIER;
Keywords:
QPSK receiver; burst transmission; timing recovery; frequency offset recovery;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
7
Recensione:
Indirizzi per estratti:
Indirizzo: Kim, SG Kwanju Inst Sci & Technol, Dept Informat & Commun, Kwangju 500712,South Korea Kwanju Inst Sci & Technol Kwangju South Korea 500712 South Korea
Citazione:
S.G. Kim et al., "Fully digital preambleless 40 Mbps QPSK receiver for burst transmission", IEICE TR EL, E84C(2), 2001, pp. 175-182

Abstract

We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about92,000 gates of Samsung KG75 SOG library which uses 0.65 mum CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.

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Documento generato il 29/09/20 alle ore 09:26:36