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Titolo:
MCM-D/C packaging solution for IBM latest S/390 servers
Autore:
Perfecto, ED; Shields, RR; Malhotra, AK; Jeanneret, MP; McHerron, DC; Katopis, GA;
Indirizzi:
IBM Corp, Microelect, Hopewell Junction, NY 12533 USA IBM Corp Hopewell Junction NY USA 12533 , Hopewell Junction, NY 12533 USA IBM Corp, Poughkeepsie, NY 12601 USA IBM Corp Poughkeepsie NY USA 12601IBM Corp, Poughkeepsie, NY 12601 USA
Titolo Testata:
IEEE TRANSACTIONS ON ADVANCED PACKAGING
fascicolo: 3, volume: 23, anno: 2000,
pagine: 515 - 520
SICI:
1521-3323(200008)23:3<515:MPSFIL>2.0.ZU;2-H
Fonte:
ISI
Lingua:
ENG
Soggetto:
POLYIMIDE; DESIGN;
Keywords:
flip chip interconnection; multichip module; pin grid array; polyimide cushion layer;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
13
Recensione:
Indirizzi per estratti:
Indirizzo: Perfecto, ED IBM Corp, Microelect, Hopewell Junction, NY 12533 USA IBM Corp Hopewell Junction NY USA 12533 nction, NY 12533 USA
Citazione:
E.D. Perfecto et al., "MCM-D/C packaging solution for IBM latest S/390 servers", IEEE T AD P, 23(3), 2000, pp. 515-520

Abstract

The G5, the most recent member of the S390 server family, was announced inMay 1998. The multichip module (MCM) at the heart of the G5 system consists of 29 CMOS chips on a 127.5 mm glass ceramic substrate with 6 levels of thin films (TF) including 1 signal plane pair. System performance of the G5 exceeds 1000 MIPS, This breakthrough performance resulted from the synergy created by combining IBM's leadership technologies in CMOS high frequency microprocessor design with advanced packaging and flip chip interconnections. From a substrate perspective, IBM moved from alumina ceramic with molybdenum (Mo) conductor to cordurite/glass ceramic, and copper (Cu) conductor, and from TF redistribution (4 levels) to TF wiring (6 levels). This paper discusses the TF implications from a change of substrate material and increased wiring density, as well as the need to implement a polyimide cushion layer as part of a pin grid array (PGA) fabrication process that supports 4224I/O's.

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Documento generato il 07/07/20 alle ore 19:06:21