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Titolo:
A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets
Autore:
Deleonibus, S; Caillat, C; Guegan, G; Heitzmann, M; Nier, ME; Tedesco, S; Dalzotto, B; Martin, F; Mur, P; Papon, AM; Lecarval, G; Biswas, S; Souil, D;
Indirizzi:
CEA Grenoble, LETI, F-38054 Grenoble 9, France CEA Grenoble Grenoble France 9 renoble, LETI, F-38054 Grenoble 9, France STMicroelect, F-38019 Grenoble, France STMicroelect Grenoble France F-38019 icroelect, F-38019 Grenoble, France Brunel Univ, Cascade Sci Ltd, Uxbridge UB8 3PH, Middx, England Brunel Univ Uxbridge Middx England UB8 3PH bridge UB8 3PH, Middx, England
Titolo Testata:
IEEE ELECTRON DEVICE LETTERS
fascicolo: 4, volume: 21, anno: 2000,
pagine: 173 - 175
SICI:
0741-3106(200004)21:4<173:A2PGLN>2.0.ZU;2-E
Fonte:
ISI
Lingua:
ENG
Keywords:
hard mask; metallurgical length; NMOSFET; pockets; tunneling dielectric; 20-nm gate length;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
12
Recensione:
Indirizzi per estratti:
Indirizzo: Deleonibus, S CEA Grenoble, LETI, F-38054 Grenoble 9, France CEA GrenobleGrenoble France 9 F-38054 Grenoble 9, France
Citazione:
S. Deleonibus et al., "A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets", IEEE ELEC D, 21(4), 2000, pp. 173-175

Abstract

We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick, We have achieved devices with real N- arsenic implanted extensions and BF2 pockets. The devices operate reasonably well down to 20-nm physical gate length, These devices are the shortest devices ever reported using a conventional architecture.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 20/09/20 alle ore 23:38:44