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Titolo:
Design-space exploration for block-processing based temporal partitioning of run-time reconfigurable systems
Autore:
Kaul, M; Vemuri, R;
Indirizzi:
Univ Cincinnati, Dept ECECS, Lab Digital Design Environm, Cincinnati, OH 45221 USA Univ Cincinnati Cincinnati OH USA 45221 nvironm, Cincinnati, OH 45221 USA
Titolo Testata:
JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
fascicolo: 2-3, volume: 24, anno: 2000,
pagine: 181 - 209
SICI:
1387-5485(200003)24:2-3<181:DEFBBT>2.0.ZU;2-U
Fonte:
ISI
Lingua:
ENG
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
40
Recensione:
Indirizzi per estratti:
Indirizzo: Kaul, M Univ Cincinnati, Dept ECECS, Lab Digital Design Environm, POB 210030, Cincinnati, OH 45221 USA Univ Cincinnati POB 210030 Cincinnati OH USA 45221 i, OH 45221 USA
Citazione:
M. Kaul e R. Vemuri, "Design-space exploration for block-processing based temporal partitioning of run-time reconfigurable systems", J VLSI S P, 24(2-3), 2000, pp. 181-209

Abstract

The reconfiguration capability of modern FPGA devices can be utilized to execute an application by partitioning it into multiple segments such that each segment is executed one after the other on the device. This division ofan application into multiple reconfigurable segments is called temporal partitioning. We present an automated temporal partitioning technique for acyclic behavior level task graphs. To be effective, any behavior-level partitioning method should ensure that each temporal partition meets the underlying resource constraints. For this, a knowledge of the implementation cost of each task on the hardware should be known. Since multiple implementationsof a task that differ in area and delay are possible, we perform design-space exploration to choose the best implementation of a task from among the available implementations. To overcome the high reconfiguration overhead of the current day FPGA devices, we propose integration of the temporal partitioning and design space exploration methodology with block-processing. Block-processing is used to process multiple blocks of data on each temporal partition so as to amortizethe reconfiguration time. We focus on applications that can be representedas task graphs that have to be executed many times over a large set of input data. We have integrated block-processing in the temporal partitioning framework so that it also influences the design point selection for each task. However, this does not exclude usage of our system for designs for whichblock-processing is not possible. For both block-processing and non block-processing designs our algorithm selects the best possible design point to minimize the execution time of the design. We present an ILP-based methodology for the integrated temporal partitioning, design space exploration and block-processing technique that is solved to optimality for small sized design problems and in an iterative constraint satisfaction approach for large sized design problems. We demonstrate with extensive experimental results for the Discrete Cosine Transform (DCT) and random graphs the validity of our approach.

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Documento generato il 07/07/20 alle ore 05:56:56