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Titolo:
Cascaded parallel oversampling sigma-delta modulators
Autore:
Wan, XS; Qin, W; Ling, XT;
Indirizzi:
Fudan Univ, Dept Elect Engn, Shanghai 200433, Peoples R China Fudan Univ Shanghai Peoples R China 200433 nghai 200433, Peoples R China
Titolo Testata:
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
fascicolo: 2, volume: 47, anno: 2000,
pagine: 156 - 161
SICI:
1057-7130(200002)47:2<156:CPOSM>2.0.ZU;2-R
Fonte:
ISI
Lingua:
ENG
Soggetto:
A/D CONVERSION;
Keywords:
cascade; converters; parallel; TIM;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
10
Recensione:
Indirizzi per estratti:
Indirizzo: Wan, XS Fudan Univ, Dept Elect Engn, Shanghai 200433, Peoples R China Fudan Univ Shanghai Peoples R China 200433 0433, Peoples R China
Citazione:
X.S. Wan et al., "Cascaded parallel oversampling sigma-delta modulators", IEEE CIR-II, 47(2), 2000, pp. 156-161

Abstract

Based on the well-known time-interleaved modulator (TIM), a new cascade-parallel architecture of oversampling sigma-delta analog-to-digital converters is proposed. While retaining the speed advantage of TIM, the new architecture gives a general method to effectively suppress the influence of circuit nonidealities, especially coefficient mismatches, on the converter's resolution. Such influence is a serious problem in the practical realization ofTIM. Simulation results of examples of both TIM and the new architecture are given for comparison, In addition to its improved performance, the new architecture turns out to be quite simple, Therefore it can be a practical approach to extend the use of sigma-delta analog-to-digital conversion to high-speed applications.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 22/09/20 alle ore 09:23:49