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Titolo:
A simulation study of decoupled vector architectures
Autore:
Espasa, R; Valero, M;
Indirizzi:
Univ Politecn Catalunya, Dept Arquitectura Comp, Barcelona, Spain Univ Politecn Catalunya Barcelona Spain itectura Comp, Barcelona, Spain
Titolo Testata:
JOURNAL OF SUPERCOMPUTING
fascicolo: 2, volume: 14, anno: 1999,
pagine: 129 - 152
SICI:
0920-8542(199909)14:2<129:ASSODV>2.0.ZU;2-L
Fonte:
ISI
Lingua:
ENG
Soggetto:
PERFORMANCE;
Keywords:
vector architectures; decoupling; instruction-level parallelism; memory latency;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
25
Recensione:
Indirizzi per estratti:
Indirizzo: Espasa, R Univ Politecn Catalunya, Dept Arquitectura Comp, Barcelona, Spain Univ Politecn Catalunya Barcelona Spain omp, Barcelona, Spain
Citazione:
R. Espasa e M. Valero, "A simulation study of decoupled vector architectures", J SUPERCOMP, 14(2), 1999, pp. 129-152

Abstract

Decoupling techniques can be applied to a vector processor, resulting in alarge increase in performance of vectorizable programs. We simulate a selection of the Perfect Club and Specfp92 benchmark suites and compare their execution time on a conventional single port vector architecture with that of a decoupled vector architecture. Decoupling increases the performance by a factor greater than 1.4 for realistic memory latencies, and for an ideal memory system with zero latency, there is still a speedup of as much as 1.3. A significant portion of this paper is devoted to studying the tradeoffs involved in choosing a suitable size for the queues of the decoupled architecture. The hardware cost of the queues need not be large to achieve most of the performance advantages of decoupling.

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Documento generato il 07/07/20 alle ore 12:22:03