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Titolo:
A 3-D stacked chip packaging solution for miniaturized massively parallel processing
Autore:
Lea, RM; Jalowiecki, IP; Boughton, DK; Yamaguchi, JS; Pepe, AA; Ozguz, VH; Carson, JC;
Indirizzi:
Brunel Univ, Uxbridge UB8 3PH, Middx, England Brunel Univ Uxbridge Middx England UB8 3PH bridge UB8 3PH, Middx, England Aspex Microsyst Ltd, Uxbridge UB8 3PH, Middx, England Aspex Microsyst LtdUxbridge Middx England UB8 3PH B8 3PH, Middx, England Irvine Sensors Corp, Costa Mesa, CA 92626 USA Irvine Sensors Corp Costa Mesa CA USA 92626 orp, Costa Mesa, CA 92626 USA
Titolo Testata:
IEEE TRANSACTIONS ON ADVANCED PACKAGING
fascicolo: 3, volume: 22, anno: 1999,
pagine: 424 - 432
SICI:
1521-3323(199908)22:3<424:A3SCPS>2.0.ZU;2-E
Fonte:
ISI
Lingua:
ENG
Keywords:
associative processing; defect/fault tolerance; high density interconnect; massively parallel processor implementation; three-dimensional (3-D) chip stacking;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
11
Recensione:
Indirizzi per estratti:
Indirizzo: Lea, RM Brunel Univ, Uxbridge UB8 3PH, Middx, England Brunel Univ Uxbridge Middx England UB8 3PH B8 3PH, Middx, England
Citazione:
R.M. Lea et al., "A 3-D stacked chip packaging solution for miniaturized massively parallel processing", IEEE T AD P, 22(3), 1999, pp. 424-432

Abstract

The development and evaluation of a three-dimensional (3-D) interconnect and packaging technology for massively parallel processor (MPP) implementation is reported. Following reviews of specific modular massively parallel computer (MPC) accelerator and chip stacking technologies, the paper reports the progress of a collaborative research project to pioneer a novel MPP module. The design of a highly compact 3-D chip-stack, integrating five MPP chips in a single package, is described in detail. Problems encountered and their solutions are reported. Test results for prototype MPP chip-stacks provide proof-of-principle for the 3-D chip stacking approach. Allowing from 2:1 to 4:1 savings in the modular MPC implementation size, without significant increase in cost or loss of performance, the emerging MPP chip stacking technology offers a cost-effective solution for MPP miniaturization.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 27/01/20 alle ore 14:23:30