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Titolo:
Design investigation of 1D-Arrays of metallic single electron tunneling transistors
Autore:
Knoll, M; Uhlmann, FH;
Indirizzi:
Tech Univ Ilmenau, D-98684 Ilmenau, Germany Tech Univ Ilmenau Ilmenau Germany D-98684 enau, D-98684 Ilmenau, Germany
Titolo Testata:
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY
fascicolo: 2, volume: 9, anno: 1999,
parte:, 3
pagine: 4265 - 4268
SICI:
1051-8223(199906)9:2<4265:DIO1OM>2.0.ZU;2-E
Fonte:
ISI
Lingua:
ENG
Soggetto:
JUNCTIONS;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Physical, Chemical & Earth Sciences
Citazioni:
10
Recensione:
Indirizzi per estratti:
Indirizzo: Knoll, M Tech Univ Ilmenau, D-98684 Ilmenau, Germany Tech Univ Ilmenau Ilmenau Germany D-98684 8684 Ilmenau, Germany
Citazione:
M. Knoll e F.H. Uhlmann, "Design investigation of 1D-Arrays of metallic single electron tunneling transistors", IEEE APPL S, 9(2), 1999, pp. 4265-4268

Abstract

Starting from the geometry and material constants we calculate the capacitances in metallic single charge tunneling structures using a 3D numerical field computation tool based on the boundary element method. This is exemplified by means of a step-edge cut-off tunnel junction geometry. Beginning with a single junction we further investigate multi-junction single electron transistors and, for the first time, arrays of them. Beside this calculation of the inter-capacitance matrix we quantitatively analyze the influence of parasitic background charges. In view of its performance our tool could establish the basis for the evaluation of more complex layouts in single charge electronics.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 04/12/20 alle ore 22:01:50