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Titolo:
A new self-aligned offset staggered polysilicon thin-film transistor
Autore:
Han, JI; Yang, GY; Han, CH;
Indirizzi:
Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea Korea Adv Inst Sci & Technol Taejon South Korea 305701 5701, South Korea
Titolo Testata:
IEEE ELECTRON DEVICE LETTERS
fascicolo: 8, volume: 20, anno: 1999,
pagine: 381 - 383
SICI:
0741-3106(199908)20:8<381:ANSOSP>2.0.ZU;2-G
Fonte:
ISI
Lingua:
ENG
Soggetto:
TFTS; GATE;
Keywords:
planarization; poly-Si TFT; PR; self-aligned off-set; staggered;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
7
Recensione:
Indirizzi per estratti:
Indirizzo: Han, JI Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea Korea Adv Inst Sci & Technol Taejon South Korea 305701 uth Korea
Citazione:
J.I. Han et al., "A new self-aligned offset staggered polysilicon thin-film transistor", IEEE ELEC D, 20(8), 1999, pp. 381-383

Abstract

A new self-aligned offset staggered polysilicon thin-film transistor (poly-Si TFT) has been proposed and demonstrated to have a suppressed leakage current. For the self-aligned offset structure, planarization with thick photoresist and etchback of photoresist are successfully utilized, The offset length can be easily controlled by the thickness of the gate material without photolithographic limitation. In the self-aligned offset polysilicon TFT's, the leakage current decreases with an increasing offset length.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 04/12/20 alle ore 09:13:08