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Titolo:
Simulation-based power estimation for low-power designs: A fractal approach
Autore:
Radjassamy, R; Carothers, JD;
Indirizzi:
Hewlett Packard Co, VLSI Technol Ctr, Tech Staff, Ft Collins, CO USA Hewlett Packard Co Ft Collins CO USA Ctr, Tech Staff, Ft Collins, CO USA Univ Arizona, Dept Elect & Comp Engn, Tucson, AZ 85721 USA Univ Arizona Tucson AZ USA 85721 Elect & Comp Engn, Tucson, AZ 85721 USA
Titolo Testata:
SIMULATION
fascicolo: 5, volume: 72, anno: 1999,
pagine: 320 - 326
SICI:
0037-5497(199905)72:5<320:SPEFLD>2.0.ZU;2-K
Fonte:
ISI
Lingua:
ENG
Keywords:
power estimation; vector compaction; compaction ratio; fractals; Hurst parameter;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
Citazioni:
14
Recensione:
Indirizzi per estratti:
Indirizzo: Radjassamy, R Hewlett Packard Co, VLSI Technol Ctr, Tech Staff, Ft Collins, CO USA Hewlett Packard Co Ft Collins CO USA f, Ft Collins, CO USA
Citazione:
R. Radjassamy e J.D. Carothers, "Simulation-based power estimation for low-power designs: A fractal approach", SIMULATION, 72(5), 1999, pp. 320-326

Abstract

Low-power CMOS integrated circuit design requires accurate power estimation at every level in the hierarchy. In this paper, the Fractal Compaction Algorithm is presented. It is based on fractal concepts and is used to generate a compared vector that allows fast, accurate simulation-based power estimation. Typically, power estimation methods are either dynamic or static. Dynamic methods simulate the design using specific input vector sets and estimate power. Though accurate, these methods require long simulation time for larger designs. Static power estimation methods, on the other hand, are based on analytical tools that estimate power quickly but with less accuracy. To achieve the accuracy of dynamic methods and the speed of static methods, one approach is to generate a compact, representative vector set with switching behavior similar to the original set. The algorithm generates a compact vector set by exploiting the correlation in the toggle distribution ofthe circuit's internal nodes. Experiments on ISCAS85 benchmark circuits with a vector set size of 4000 results in a compaction of 65.57X (max) and 38.14X (avg) with power estimation error of 2.40% (max) and 2.06% (avg). The reduction in simulation time translates into a shorter design phase and quicker tape out. Compaction results for various vector sizes are also presented.

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Documento generato il 20/09/20 alle ore 10:37:34