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Titolo:
Performance enhancement of multistage interconnection networks with unit step buffering
Autore:
Youn, HY; Cho, H;
Indirizzi:
Univ Texas, Dept Comp Sci & Engn, Arlington, TX 76019 USA Univ Texas Arlington TX USA 76019 omp Sci & Engn, Arlington, TX 76019 USA
Titolo Testata:
IEEE TRANSACTIONS ON COMMUNICATIONS
fascicolo: 4, volume: 47, anno: 1999,
pagine: 618 - 630
SICI:
0090-6778(199904)47:4<618:PEOMIN>2.0.ZU;2-C
Fonte:
ISI
Lingua:
ENG
Keywords:
ATM switching; delay; multistage interconnection networks; throughput; unit step buffering;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
18
Recensione:
Indirizzi per estratti:
Indirizzo: Youn, HY Univ Texas, Dept Comp Sci & Engn, Arlington, TX 76019 USA Univ Texas Arlington TX USA 76019 Engn, Arlington, TX 76019 USA
Citazione:
H.Y. Youn e H. Cho, "Performance enhancement of multistage interconnection networks with unit step buffering", IEEE COMMUN, 47(4), 1999, pp. 618-630

Abstract

Multistage interconnection network (MIN) has been widely used for parallelcomputer systems, and also recognized as an efficient switching fabric fordigital communication. In this paper, we propose a new switching mechanismfor MIN's called unit step buffering (USB) which significantly improves the network performance. Here each cell is allowed to move only one buffer entry position using short network cycle. The proposed USE scheme is comparedto the traditional scheme by analytical modeling and computer simulation, They reveal that throughput and delay are improved about 60%-80% for practical size MIN's with reasonable traffic in asynchronous transfer mode (ATM) switching environment, Improvement on parallel computer systems with largersize packets is more significant as about 100%, More importantly, the scheme does not require any additional hardware or operational overhead.

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Documento generato il 27/11/20 alle ore 22:20:00