Catalogo Articoli (Spogli Riviste)

OPAC HELP

Titolo:
A LOW-POWER VLSI ARCHITECTURE FOR FULL-SEARCH BLOCK-MATCHING MOTION ESTIMATION
Autore:
DO VL; YUN KY;
Indirizzi:
UNIV CALIF SAN DIEGO,DEPT ELECT & COMP ENGN LA JOLLA CA 92093
Titolo Testata:
IEEE transactions on circuits and systems for video technology
fascicolo: 4, volume: 8, anno: 1998,
pagine: 393 - 398
SICI:
1051-8215(1998)8:4<393:ALVAFF>2.0.ZU;2-S
Fonte:
ISI
Lingua:
ENG
Keywords:
FULL-SEARCH BLOCK MATCHING; LOW POWER; VLSI MOTION ESTIMATION;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Science Citation Index Expanded
Citazioni:
11
Recensione:
Indirizzi per estratti:
Citazione:
V.L. Do e K.Y. Yun, "A LOW-POWER VLSI ARCHITECTURE FOR FULL-SEARCH BLOCK-MATCHING MOTION ESTIMATION", IEEE transactions on circuits and systems for video technology, 8(4), 1998, pp. 393-398

Abstract

This paper presents an architectural enhancement to reduce the power consumption Of the full-search block-matching (FSBM) motion estimation. Our approach is based on eliminating unnecessary computation using conservative approximation, Augmenting the estimation technique to a conventional systolic-architecture-based VLSI motion estimation reduces the power consumption by a factor of 2, while still preserving the optimal solution and the throughput. A register-transfer level implementation as welt as simulation results on benchmark video clips are presented.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 14/07/20 alle ore 22:57:18