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Titolo:
FRONT-END MODULE READOUT AND CONTROL ELECTRONICS FOR THE PHENIX MULTIPLICITY VERTEX DETECTOR
Autore:
ERICSON MN; ALLEN MD; BOISSEVAIN J; BRITTON CL; EMERY MS; HAHN SF; KAPUSTINSKY JS; LIND RE; MUSROCK MS; SIMONGILLO J; SMITH DE; SULLIVAN JP; VANHECKE H; YOUNG GR; SMITH MC;
Indirizzi:
OAK RIDGE NATL LAB OAK RIDGE TN 37831 LOS ALAMOS NATL LAB LOS ALAMOS NM 87545 UNIV TENNESSEE KNOXVILLE TN 37996
Titolo Testata:
IEEE transactions on nuclear science
fascicolo: 3, volume: 45, anno: 1998,
pagine: 833 - 837
SICI:
0018-9499(1998)45:3<833:FMRACE>2.0.ZU;2-D
Fonte:
ISI
Lingua:
ENG
Soggetto:
ANALOG;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Science Citation Index Expanded
Science Citation Index Expanded
Citazioni:
8
Recensione:
Indirizzi per estratti:
Citazione:
M.N. Ericson et al., "FRONT-END MODULE READOUT AND CONTROL ELECTRONICS FOR THE PHENIX MULTIPLICITY VERTEX DETECTOR", IEEE transactions on nuclear science, 45(3), 1998, pp. 833-837

Abstract

Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout,formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and datareadout needs of the MVD. Unit functioning, interfaces, control timing, data format, and communication rates will be Fiber discussed in detail. Tn addition, subsystem issues regarding mode control, serial architecture and functions, error handling, Global and FPGA implementationand programming will be presented.

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Documento generato il 02/12/20 alle ore 03:38:34