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Titolo:
SCR: SPICE netlist reduction tool
Autore:
Kuribayashi, M; Yamada, M; Takeuchi, H; Murakata, M;
Indirizzi:
ToshibanCorp, Semicond DA & Test Engn Ctr, Kawasaki, Kanagawa 2108520, Japa Toshiba Corp Kawasaki Kanagawa Japan 2108520 saki, Kanagawa 2108520, Japa
Titolo Testata:
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
fascicolo: 3, volume: E82A, anno: 1999,
pagine: 417 - 423
SICI:
0916-8508(199903)E82A:3<417:SSNRT>2.0.ZU;2-I
Fonte:
ISI
Lingua:
ENG
Keywords:
SPICE; reduction; transistor; simulation; CAD; VLSI;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Engineering, Computing & Technology
--discip_EC--
Citazioni:
6
Recensione:
Indirizzi per estratti:
Indirizzo: Kuribayashi, M ToshibanCorp, Semicond DA & Test Engn Ctr, Kawasaki, Kanagawa 2108520, Japa Toshiba Corp Kawasaki Kanagawa Japan 2108520 2108520, Japa
Citazione:
M. Kuribayashi et al., "SCR: SPICE netlist reduction tool", IEICE T FUN, E82A(3), 1999, pp. 417-423

Abstract

This paper describes an efficient SPICE netlist reduction method, which enables collective simulation of large circuits. The method reduces a SPICE netlist to only those devices which affect the simulation results. Parts of the netlist can be significantly reduced in size; with relatively discrepancies arising between the original SPICE simulation and the reduced SPICE simulation. The authors' reduction method is more general than previous works, since it reduces circuits using the features of MOS transistors. According to experimental results, reduction rates can range from 1/2 to 1/223. Depending on the reduction, the time taken time to run a SPICE simulation was reduced by between one and two oder of magnitude. Using this method and working on the reduced netlist, SPICE could even handle netlist for very largecircuits which it could not ordinarily handle. The simulation error between the original SPICE simulation and the reduced SPICE simulation was about 3.5%.

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Documento generato il 07/07/20 alle ore 11:36:17