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Titolo:
NOVEL STACKED CAPACITOR TECHNOLOGY FOR 1-GBIT DRAMS WITH (BA,SR)TIO3 THIN-FILMS
Autore:
HORIKAWA T; YUUKI A; SHIBANO T; KAWAHARA T; MAKITA T; KUROIWA T; YAMAMUKA M; OOMORI T; MIKAMI N; ONO K;
Indirizzi:
MITSUBISHI ELECTR CORP,ADV TECHNOL R&D CTR,ADV ULSI TECHNOL DEPT AMAGASAKI HYOGO 661 JAPAN MITSUBISHI ELECTR CORP,STRATEG R&D PLANNING GRP,ADV TECHNOL R&D CTR AMAGASAKI HYOGO 661 JAPAN
Titolo Testata:
Electronics & communications in Japan. Part 2, Electronics
fascicolo: 5, volume: 80, anno: 1997,
pagine: 70 - 78
SICI:
8756-663X(1997)80:5<70:NSCTF1>2.0.ZU;2-F
Fonte:
ISI
Lingua:
ENG
Soggetto:
CHEMICAL-VAPOR-DEPOSITION; ELECTRICAL-PROPERTIES;
Keywords:
STACKED CAPACITOR TECHNOLOGY; 1-GBIT DRAM; (BA,SR)TIO3 THIN FILM; BST FILM; STACKED CELL CAPACITOR;
Tipo documento:
Article
Natura:
Periodico
Citazioni:
21
Recensione:
Indirizzi per estratti:
Citazione:
T. Horikawa et al., "NOVEL STACKED CAPACITOR TECHNOLOGY FOR 1-GBIT DRAMS WITH (BA,SR)TIO3 THIN-FILMS", Electronics & communications in Japan. Part 2, Electronics, 80(5), 1997, pp. 70-78

Abstract

Novel stacked cell capacitors with (Ba,Sr)TiO3 (BST) films were prepared as dielectrics for Gbit-scale DRAMs. The BST films were deposited by the liquid source chemical vapor deposition (CVD) method, and Ru was used as an electrode material for storage nodes and cell plates. ForBST films on Ru electrodes, a two-step film deposition process by repetition of low-temperature deposition and subsequent-high temperature annealing was shown to result in smooth surface morphology and conformal step coverage; in addition, no residues were formed on the mask side walls during Ru etching in oxygen-containing plasmas. The surfaces of the Ru electrodes were not oxidized during the BST deposition and annealing process, and these results indicate that Ru is a most possiblematerial for capacitor electrodes, The electrical properties obtainedfor the 25-nm-thick BST films on Ru electrodes are: leak current density 2 x 10(-8) A/cm(2), silicon dioxide equivalent thickness 0.5 nm. Using these techniques, minute stacked capacitors were fabricated with storage nodes 0.24 mu m wide, 0.60 mu m deep, and 0.2 mu m high (spaced 0.14 mm apart), and their applicability for 1-Gbit DRAM memory cellswas examined. (C) 1997 Scripta Technica, Inc.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 29/10/20 alle ore 06:06:58