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Titolo:
CONFLICT-FREE ACCESS FOR STREAMS IN MULTIMODULE MEMORIES
Autore:
VALERO M; LANG T; PEIRON M; AYGUADE E;
Indirizzi:
UNIV POLITECN CATALUNYA,DEPT ARQUITECTURA COMP,C GRAN CAPITA S-N,MODUL D6 E-08071 BARCELONA SPAIN UNIV CALIF IRVINE,DEPT ELECT & COMP ENGN IRVINE CA 92717
Titolo Testata:
I.E.E.E. transactions on computers
fascicolo: 5, volume: 44, anno: 1995,
pagine: 634 - 646
SICI:
0018-9340(1995)44:5<634:CAFSIM>2.0.ZU;2-E
Fonte:
ISI
Lingua:
ENG
Soggetto:
VECTOR; PROCESSOR; SYSTEMS;
Keywords:
CONFLICT-FREE ACCESS; DECOUPLED ACCESS; MULTIMODULE MEMORIES; OUT-OF-ORDER ACCESS; STORAGE SCHEMES; STREAMS WITH CONSTANT STRIDES; VECTOR PROCESSORS;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
CompuMath Citation Index
Science Citation Index Expanded
Science Citation Index Expanded
Citazioni:
17
Recensione:
Indirizzi per estratti:
Citazione:
M. Valero et al., "CONFLICT-FREE ACCESS FOR STREAMS IN MULTIMODULE MEMORIES", I.E.E.E. transactions on computers, 44(5), 1995, pp. 634-646

Abstract

Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access for streams with constant stride. However, this is achieved only for some strides,In this paper, we extend these schemes to achieve this conflict- freeaccess for a larger number of strides, The basic idea is to perform an out-of-order access to a stream of fixed length, This stream is thenstored in a local memory and used in subsequent instructions, This mode of operation is suitable for vector processors and for processors with decoupled access. The scheme and mode of operation proposed produce the largest possible number of conflict-free strides, Memory systemswith any ratio between the number of memory modules and memory latency are considered, The hardware for address calculations and access control is described and shown to be of similar complexity as that required for access in order.

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Documento generato il 06/08/20 alle ore 00:34:05