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Titolo:
A 32-BIT LOGARITHMIC NUMBER SYSTEM PROCESSOR
Autore:
HUANG SC; CHEN LG; CHEN TH;
Indirizzi:
NATL TAIWAN UNIV,DEPT ELECT ENGN TAIPEI 10764 TAIWAN NAN TAI INST TECHNOL,DEPT ELECT ENGN TAINAN TAIWAN
Titolo Testata:
Journal of VLSI signal processing systems for signal, image, and video technology
fascicolo: 3, volume: 14, anno: 1996,
pagine: 311 - 319
SICI:
1387-5485(1996)14:3<311:A3LNSP>2.0.ZU;2-X
Fonte:
ISI
Lingua:
ENG
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
CompuMath Citation Index
Science Citation Index Expanded
Science Citation Index Expanded
Citazioni:
11
Recensione:
Indirizzi per estratti:
Citazione:
S.C. Huang et al., "A 32-BIT LOGARITHMIC NUMBER SYSTEM PROCESSOR", Journal of VLSI signal processing systems for signal, image, and video technology, 14(3), 1996, pp. 311-319

Abstract

To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log(2)(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 2(Ox) function. The basic concept behind DP is that variable x can be divided into two parts in bit representation to be implemented. Thus, ROM or PLA table can be reduced to a reasonable size and this will make a high precision design allowable. The basic idea of IDLA is that the function 2(Ox) can be obtained approximately through iterative linear approximations. By this method, only adder, shifter anda small PLA are required, unlike the previous designs which require ROM and multiplier. The experiment results reveal that the proposed design is more attractive than the previous researches in the LNS processor.

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Documento generato il 01/04/20 alle ore 01:47:32