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Titolo:
MODELING OF VLSI RC PARASITICS BASED ON THE NETWORK REDUCTION ALGORITHM
Autore:
NIEWCZAS M; WOJTASIK A;
Indirizzi:
WARSAW UNIV TECHNOL,INST MICROELECTR & OPTOELECTR PL-00662 WARSAW POLAND
Titolo Testata:
IEEE transactions on computer-aided design of integrated circuits and systems
fascicolo: 2, volume: 14, anno: 1995,
pagine: 137 - 144
SICI:
0278-0070(1995)14:2<137:MOVRPB>2.0.ZU;2-Z
Fonte:
ISI
Lingua:
ENG
Soggetto:
CAPACITANCE; FORMULAS;
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
CompuMath Citation Index
Science Citation Index Expanded
Citazioni:
16
Recensione:
Indirizzi per estratti:
Citazione:
M. Niewczas e A. Wojtasik, "MODELING OF VLSI RC PARASITICS BASED ON THE NETWORK REDUCTION ALGORITHM", IEEE transactions on computer-aided design of integrated circuits and systems, 14(2), 1995, pp. 137-144

Abstract

This paper presents a method of modeling of R and C parasitics in VLSI circuits. A network representation is generated for finite difference discretization of 2-D Laplace's equation, and a reduction algorithm is applied to this network, The solution area can be defined by any set of polygons. If n is the number of discretization nodes the new algorithm is O(n(1.5)). It yields directly the coefficients of capacitanceor admittance matrix. In contrast to other methods, in the network reduction approach, the time required for modeling depends mainly upon the complexity of the solution area but weakly upon the number of terminals. This feature is particularly valuable in application to circuit extraction.

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Documento generato il 28/10/20 alle ore 19:40:09