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Titolo:
CACHE WRITE GENERATE FOR PARALLEL IMAGE-PROCESSING ON SHARED-MEMORY ARCHITECTURES
Autore:
WITTENBRINK CM; SOMANI AK; CHEN CH;
Indirizzi:
UNIV CALIF SANTA CRUZ,BASKIN CTR COMP ENGN SANTA CRUZ CA 95064 UNIV WASHINGTON,DEPT ELECT ENGN SEATTLE WA 98195
Titolo Testata:
IEEE transactions on image processing
fascicolo: 7, volume: 5, anno: 1996,
pagine: 1204 - 1208
SICI:
1057-7149(1996)5:7<1204:CWGFPI>2.0.ZU;2-D
Fonte:
ISI
Lingua:
ENG
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Science Citation Index Expanded
Citazioni:
10
Recensione:
Indirizzi per estratti:
Citazione:
C.M. Wittenbrink et al., "CACHE WRITE GENERATE FOR PARALLEL IMAGE-PROCESSING ON SHARED-MEMORY ARCHITECTURES", IEEE transactions on image processing, 5(7), 1996, pp. 1204-1208

Abstract

We investigate cache write generate, our cache mode invention. We demonstrate that for parallel image processing applications, the new modeimproves main memory bandwidth, CPU efficiency, cache hits, and cachelatency. We use register level simulations validated by the UW-Proteus system. Many memory, cache, and processor configurations are evaluated.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 31/03/20 alle ore 19:41:13