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Titolo:
A JOSEPHSON BUILT-IN SELF-TESTING (JBIST) SYSTEM FOR GIGAHERTZ FUNCTIONAL TESTS OF JOSEPHSON RAMS
Autore:
HASHIMOTO Y; TAHARA S; NAGASAWA S; NUMATA H; KATO C; AOYAGI M; NAKAGAWA H; KUROSAWA I; TAKADA S;
Indirizzi:
NEC CORP LTD,FUNDAMENTAL RES LABS,34 MIYUKIGAOKA TSUKUBA IBARAKI 305 JAPAN ELECTROTECH LAB TSUKUBA IBARAKI 305 JAPAN
Titolo Testata:
Superconductor science and technology
fascicolo: 4A, volume: 9, anno: 1996,
pagine: 50 - 54
SICI:
0953-2048(1996)9:4A<50:AJBS(S>2.0.ZU;2-U
Fonte:
ISI
Lingua:
ENG
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Science Citation Index Expanded
Science Citation Index Expanded
Citazioni:
7
Recensione:
Indirizzi per estratti:
Citazione:
Y. Hashimoto et al., "A JOSEPHSON BUILT-IN SELF-TESTING (JBIST) SYSTEM FOR GIGAHERTZ FUNCTIONAL TESTS OF JOSEPHSON RAMS", Superconductor science and technology, 9(4A), 1996, pp. 50-54

Abstract

We propose a Josephson built-in self-testing (JBIST) system. The aim of the JBIST system is to perform functional tests for Josephson RAMs at more than 1 GHz. The prototype JBIST circuit is designed for a 256 bit Josephson RAM, and consists of an instruction ROM and a processingcircuit. A MARCHING test program is written into the instruction ROM,and the processing circuit executes the program on the instruction ROM. Total power consumption of the JBIST circuit is designed to be 4.2 mW. Estimated delays for the critical paths suggest the potential of agigahertz clock testing. We fabricated the JBIST circuit chips by using Nb-AIO(x)-Nb Josephson junctions. The component circuits in the JBIST circuit (sequence controller, comparator, and instruction ROM) are successfully operated.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 20/09/20 alle ore 10:37:22