Catalogo Articoli (Spogli Riviste)

OPAC HELP

Titolo:
A 64-B MICROPROCESSOR WITH MULTIMEDIA SUPPORT
Autore:
LEV LA; CHARNAS A; TREMBLAY M; DALAL AR; FREDERICK BA; SRIVATSA CR; GREENHILL D; WENDELL DL; PHAM DD; ANDERSON E; HINGARH HK; RAZZACK I; KAKU JM; SHIN K; LEVITT ME; ALLEN M; FEROLITO PA; BARTOLOTTI RL; YU RK; MELANSON RJ; SHAH SI; NGUYEN S; MITRA SS; REDDY V; GANESAN V; DELANGE WJ;
Indirizzi:
SUN MICROSYST INC MT VIEW CA 94043
Titolo Testata:
IEEE journal of solid-state circuits
fascicolo: 11, volume: 30, anno: 1995,
pagine: 1227 - 1238
SICI:
0018-9200(1995)30:11<1227:A6MWMS>2.0.ZU;2-7
Fonte:
ISI
Lingua:
ENG
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Science Citation Index Expanded
Citazioni:
15
Recensione:
Indirizzi per estratti:
Citazione:
L.A. Lev et al., "A 64-B MICROPROCESSOR WITH MULTIMEDIA SUPPORT", IEEE journal of solid-state circuits, 30(11), 1995, pp. 1227-1238

Abstract

A 167 MHz 64 b VLSI CPU chip is described. The chip executes a 333-MFLOPS (peak) with an estimated system performance of 270SPECint92/380SPECfp92 (@167 MHz, 2 MB E-cache). The 17.7 x 17.8 mm die is fabricated with a 0.5 micron CMOS technology with four metal layers and contains 5.2 M transistors. The superscalar processor is capable of sustaining an execution rate of four instructions per cycle even in the presence of conditional branches and cache misses. Four fully pipelined 8 x 16 b multipliers and four single-cycle latency 16 b adders combine to speed up image processing, 2-D, 3-D graphics, video compression/decompression by up to an order of magnitude. High clock speed was obtained by the use of delayed reset logic, a new register file design, and novel comparators. Strict design methodology allowed fully functional first silicon which met all speed targets. The power dissipation of the chipis 28 W.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 10/07/20 alle ore 03:15:59