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Titolo:
A FULLY PROGRAMMABLE SYSTOLIC PIPELINED DIGITAL VIDEO ENCODER FOR NTSC PAL/PALPLUS COMPATIBILITY ON A 4/3 SCREEN/
Autore:
OH SH; CHOI HJ; KWON SW; LEE MK;
Indirizzi:
YONSEI UNIV,DEPT ELECT ENGN,VLSI & CAD LAB SEOUL 120749 SOUTH KOREA
Titolo Testata:
IEEE transactions on consumer electronics
fascicolo: 3, volume: 43, anno: 1997,
pagine: 965 - 971
SICI:
0098-3063(1997)43:3<965:AFPSPD>2.0.ZU;2-#
Fonte:
ISI
Lingua:
ENG
Tipo documento:
Article
Natura:
Periodico
Settore Disciplinare:
Science Citation Index Expanded
Science Citation Index Expanded
Citazioni:
10
Recensione:
Indirizzi per estratti:
Citazione:
S.H. Oh et al., "A FULLY PROGRAMMABLE SYSTOLIC PIPELINED DIGITAL VIDEO ENCODER FOR NTSC PAL/PALPLUS COMPATIBILITY ON A 4/3 SCREEN/", IEEE transactions on consumer electronics, 43(3), 1997, pp. 965-971

Abstract

A proposed encoder supports NTSC and PAL systems. In addition, it also permits PALplus standard made compatible to 16:9 wide screen on a 4:3 screen. In order for this to be realized, vertical and horizontal synchronous timings are fully programmable and the encoder is designed in systolic pipelined architecture with double pixel clock to increase an internal processing speed. Also, we have mainly concentrated on reducing the gate counts of the submodules such as letter-box converter, color converter matrix, low pass filter, interpolator, and color modulator. The encoder can accept RGB and YCbCr as the input pixel signal type in the speed of 10-15Mpps. Outputs are a Y/C (S-video) signal and a composite signal. We have modeled the encoder in Verilog-HDL and verified its overall operation by feeding the Top module with color bar test signal. Result which was implemented by 0.6um CMOS technology shows that the encoder contains about 42k gates in it.

ASDD Area Sistemi Dipartimentali e Documentali, Università di Bologna, Catalogo delle riviste ed altri periodici
Documento generato il 24/09/20 alle ore 09:25:25